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Sumio Morioka
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2020 – today
- 2023
- [c21]Maki Yoshida, Sumio Morioka, Satoshi Obana:
Secure Communication via GNSS-based Key Synchronization. WIPHAL 2023 - 2022
- [c20]Maki Yoshida, Sumio Morioka
, Satoshi Obana:
On Cryptographic Algorithms and Key Length for Delayed Disclosure Authentication of GNSS. ICL-GNSS 2022: 1-6 - 2021
- [j5]Rei Ueno
A Systematic Design Methodology of Formally Proven Side-Channel-Resistant Cryptographic Hardware. IEEE Des. Test 38(3): 84-92 (2021) - 2020
- [j4]Kosei Sakamoto, Kazuhiko Minematsu, Nao Shibata, Maki Shigeri, Hiroyasu Kubo, Yuki Funabiki, Andrey Bogdanov
Tweakable TWINE: Building a Tweakable Block Cipher on Generalized Feistel Structure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(12): 1629-1639 (2020) - [j3]Rei Ueno
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Trans. Computers 69(4): 534-548 (2020)
2010 – 2019
- 2019
- [c19]Kosei Sakamoto, Kazuhiko Minematsu, Nao Shibata, Maki Shigeri, Hiroyasu Kubo, Yuki Funabiki, Andrey Bogdanov
Tweakable TWINE: Building a Tweakable Block Cipher on Generalized Feistel Structure. IWSEC 2019: 129-145 - 2017
- [j2]Rei Ueno, Naofumi Homma, Takafumi Aoki, Sumio Morioka
Hierarchical Formal Verification Combining Algebraic Transformation with PPRM Expansion and Its Application to Masked Cryptographic Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1396-1408 (2017) - [c18]Rei Ueno, Naofumi Homma, Sumio Morioka
Automatic generation of formally-proven tamper-resistant Galois-field multipliers based on generalized masking scheme. DATE 2017: 978-983 - 2016
- [c17]Rei Ueno, Sumio Morioka
A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation. CHES 2016: 538-558 - [i2]Rei Ueno, Sumio Morioka, Naofumi Homma, Takafumi Aoki:
A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation. IACR Cryptol. ePrint Arch. 2016: 595 (2016) - 2014
- [c16]Tetsu Iwata, Kazuhiko Minematsu, Jian Guo
CLOC: Authenticated Encryption for Short Input. FSE 2014: 149-167 - [c15]Kotaro Okamoto, Naofumi Homma, Takafumi Aoki, Sumio Morioka
A hierarchical formal approach to verifying side-channel resistant cryptographic processors. HOST 2014: 76-79 - [i1]Tetsu Iwata, Kazuhiko Minematsu, Jian Guo, Sumio Morioka:
CLOC: Authenticated Encryption for Short Input. IACR Cryptol. ePrint Arch. 2014: 157 (2014) - 2012
- [c14]Tomoyasu Suzaki, Kazuhiko Minematsu, Sumio Morioka
$\textnormal{\textsc{TWINE}}$ : A Lightweight Block Cipher for Multiple Platforms. Selected Areas in Cryptography 2012: 339-354 - 2011
- [c13]Sumio Morioka
Flexible architecture optimization and ASIC implementation of group signature algorithm using a customized HLS methodology. HOST 2011: 57-62
2000 – 2009
- 2004
- [j1]Sumio Morioka
A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. IEEE Trans. Very Large Scale Integr. Syst. 12(7): 686-691 (2004) - 2003
- [c12]Akashi Satoh, Sumio Morioka
Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia. CHES 2003: 304-318 - [c11]Akashi Satoh, Sumio Morioka
Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES. ISC 2003: 252-266 - 2002
- [c10]Sumio Morioka
An Optimized S-Box Circuit Architecture for Low Power AES Design. CHES 2002: 172-186 - [c9]Sumio Morioka
A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture. ICCD 2002: 98-103 - [c8]Akashi Satoh, Sumio Morioka:
Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI. ISC 2002: 48-62 - 2001
- [c7]Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji Munetoh
A Compact Rijndael Hardware Architecture with S-Box Optimization. ASIACRYPT 2001: 239-254 - [c6]Sumio Morioka
Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m). CAV 2001: 465-477 - 2000
- [c5]Yasunao Katayama, Yasushi Negishi, Sumio Morioka
Efficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs. DFT 2000: 201- - [c4]Yasunao Katayama, Sumio Morioka
One-Shot Reed-Solomon Decoding for High-Performance Dependable Systems. DSN 2000: 390-399
1990 – 1999
- 1999
- [c3]Yasunao Katayama, Eric J. Stuckey, Sumio Morioka
Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention. DFT 1999: 311-318 - [c2]Sumio Morioka
Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder. ICCD 1999: 60-67 - 1994
- [c1]Junji Kitamichi, Sumio Morioka
Automatic Correctness Proof of the Implementation of Synchronous Sequential Circuits Using an Algebraic Approach. TPCD 1994: 165-184
Coauthor Index
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