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Nobuyoshi Nomizu
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1990 – 1999
- 1991
- [c6]Ko Yoshikawa
, Hiroshi Ichiryu, Hisato Tanishita, Shigenobu Suzuki, Nobuyoshi Nomizu, Akira Kondoh:
Timing Optimization on Mapped Circuits. DAC 1991: 112-117 - 1990
- [c5]Kaname Kuroki, Nobuyoshi Nomizu, Shigenobu Suzuki, Kazutoshi Takahashi:
A Framework Environment for Logic Design Support System. ICCAD 1990: 556-559 - [c4]Shigeru Takasaki, Nobuyoshi Nomizu, Yoshihiro Hirabayashi, Hiroshi Ishikura, Masahiro Kurashita, Nobuhiko Koike, Toshiyuki Nakata:
HAL III: function level hardware logic simulation. ICCD 1990: 167-170
1980 – 1989
- 1987
- [j1]Shigeru Takasaki, Tohru Sasaki, Nobuyoshi Nomizu, Nobuhiko Koike, Kenji Ohmori:
Block-Level Hardware Logic Simulation Machine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(1): 46-54 (1987) - 1986
- [c3]Shigeru Takasaki, Tohru Sasaki, Nobuyoshi Nomizu, Hiroshi Ishikura, Nobuhiko Koike:
HAL II: a mixed level hardware logic simulation system. DAC 1986: 581-587 - 1984
- [c2]Tohru Sasaki, Shunichi Kato, Nobuyoshi Nomizu, Hidetoshi Tanaka:
Logic Design Verification Using Automated Test Generation. ITC 1984: 88-95 - 1980
- [c1]Tohru Sasaki, Akihiko Yamada, Shunichi Kato, Terufumi Nakazawa, Kyoji Tomita, Nobuyoshi Nomizu:
MIXS: A mixed level simulator for large digital system logic verification. DAC 1980: 626-633
Coauthor Index
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