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Wonsik Yu
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2020 – today
- 2023
- [c5]Jusung Lee, Youngwoo Jo, Wonsik Yu, WooSeok Kim, Michael Choi, Sanghune Park, Jongshin Shin:
A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL. CICC 2023: 1-2 - 2022
- [c4]Dokyung Lim, Sounghun Shin, Seungmin Lee, Kihyun Kwon, Jeongmin An, Wonsik Yu, Chanyoung Jeong, WooSeok Kim, Michael Choi, Jongshin Shin:
Clock Generator with IS026262 ASIL-D Grade Safety Mechanism for SoC Clocking Application. ISSCC 2022: 210-212
2010 – 2019
- 2019
- [j7]Dongin Kim, KwangSeok Kim, Wonsik Yu, SeongHwan Cho
:
A Second-Order ΔΣ Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1643-1647 (2019) - 2015
- [j6]Wonsik Yu, KwangSeok Kim, SeongHwan Cho:
A 0.22 ps rms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter. IEEE J. Solid State Circuits 50(5): 1251-1262 (2015) - [j5]Jungho Kim, Young-Hwa Kim, KwangSeok Kim, Wonsik Yu, SeongHwan Cho:
A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs 62-II(7): 631-635 (2015) - 2014
- [j4]KwangSeok Kim, Wonsik Yu, SeongHwan Cho:
A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register. IEEE J. Solid State Circuits 49(4): 1007-1016 (2014) - [j3]Wonsik Yu, KwangSeok Kim, SeongHwan Cho:
A 148fsrms Integrated Noise 4 MHz Bandwidth Second-Order ΔΣ Time-to-Digital Converter With Gated Switched-Ring Oscillator. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2281-2289 (2014) - 2013
- [j2]KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, SeongHwan Cho:
A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier. IEEE J. Solid State Circuits 48(4): 1009-1017 (2013) - [j1]Wonsik Yu, Jaewook Kim, KwangSeok Kim, SeongHwan Cho:
A Time-Domain High-Order MASH ΔΣ ADC Using Voltage-Controlled Gated-Ring Oscillator. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(4): 856-866 (2013) - [c3]Wonsik Yu, KwangSeok Kim, SeongHwan Cho:
A 148fsrms integrated noise 4MHz bandwidth all-digital second-order ΔΣ time-to-digital converter using gated switched-ring oscillator. CICC 2013: 1-4 - 2012
- [c2]KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, SeongHwan Cho:
A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier. VLSIC 2012: 192-193 - 2011
- [c1]Jaewook Kim, Wonsik Yu, Hyun-Kyu Yu, SeongHwan Cho:
A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS. ISSCC 2011: 176-178
Coauthor Index
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