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Shenggang Chen
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2010 – 2019
- 2019
- [j7]Sheng Ma
, Zhong Liu, Shenggang Chen, Libo Huang, Yang Guo, Zhiying Wang, Meidi Zhang:
Coordinated DMA: Improving the DRAM Access Efficiency for Matrix Multiplication. IEEE Trans. Parallel Distributed Syst. 30(10): 2148-2164 (2019) - [c11]Boqian Wang, Zhonghai Lu, Shenggang Chen:
ANN Based Admission Control for On-Chip Networks. DAC 2019: 46 - [c10]Sheng Ma, Yang Guo, Shenggang Chen, Libo Huang, Zhiying Wang:
Improving the DRAM Access Efficiency for Matrix Multiplication on Multicore Accelerators. DATE 2019: 1058-1063 - [c9]Shenggang Chen, Zhonghai Lu:
Hardware Acceleration of Multilayer Perceptron Based on Inter-Layer Optimization. ICCD 2019: 164-172 - 2016
- [j6]Yaohua Wang, Dong Wang, Shuming Chen, Zonglin Liu, Shenggang Chen, Xiaowen Chen, Xu Zhou:
Iteration Interleaving-Based SIMD Lane Partition. ACM Trans. Archit. Code Optim. 12(4): 58:1-58:18 (2016) - [c8]Xiaowen Chen, Zhonghai Lu, Yuanwu Lei, Yaohua Wang, Shenggang Chen:
Multi-bit transient fault control for NoC links using 2D fault coding method. NOCS 2016: 1-8 - 2015
- [j5]Chen Li, Sheng Ma, Shenggang Chen, Yang Guo, Peng Wang:
Express Ring: a multi-layer and non-blocking NoC architecture. IEICE Electron. Express 12(3): 20141190 (2015) - [j4]Xiaowen Chen, Zhonghai Lu, Axel Jantsch
Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications. J. Electr. Comput. Eng. 2015: 902591:1-902591:20 (2015) - [j3]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo, Shenggang Chen, Hu Chen, Man Liao:
Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips. J. Softw. 10(2): 142-161 (2015) - [c7]Xiaowen Chen, Zhonghai Lu, Yang Li, Axel Jantsch
Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs. ISVLSI 2015: 398-403 - 2013
- [j2]Xiaowen Chen, Zhonghai Lu, Axel Jantsch
Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property. Comput. Electr. Eng. 39(2): 596-612 (2013) - 2011
- [c6]Shuming Chen, Xiaowen Chen, Yi Xu, Jianghua Wan, Jianzhuang Lu, Xiangyuan Liu, Shenggang Chen:
Design and chip implementation of a heterogeneous multi-core DSP. ASP-DAC 2011: 91-92 - [c5]Yaohua Wang, Shuming Chen, Jianghua Wan, Kai Zhang, Shenggang Chen:
AIFSP: An Adaptive Instruction Flow Stream Processor. ISVLSI 2011: 272-277 - [c4]Sheng Liu, Shuming Chen, Haiyan Chen, Shenggang Chen, Hu Chen:
Supporting Efficient Memory Conflicts Reduction Using the DMA Cache Technique in Vector DSPs. NAS 2011: 302-308 - 2010
- [j1]Shenggang Chen, Shuming Chen, Shuwei Sun:
P3-CABAC: A Nonstandard Tri-Thread Parallel Evolution of CABAC in the Manycore Era. IEEE Trans. Circuits Syst. Video Technol. 20(6): 920-924 (2010) - [c3]Shenggang Chen, Shuming Chen, Huitao Gu, Hu Chen, Yaming Yin, Xiaowen Chen, Shuwei Sun, Sheng Liu, Yaohua Wang:
Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform. HPCC 2010: 465-470 - [c2]Shenggang Chen, Shuming Chen, Yaming Yin:
Performance impact of SMP-cluster on the On-chip Large-scale Parallel Computing architecture. IPDPS Workshops 2010: 1-7 - [c1]Huitao Gu, Shuming Chen, Shuwei Sun, Shenggang Chen, Xiaowen Chen:
Multiple Search Centers Based Fast Motion Estimation Algorithm for H.264/AVC. PDCAT 2010: 346-350
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