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Arrvindh Shriraman
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2020 – today
- 2024
- [c39]Anagha Molakalmur Anil Kumar
, Aditya Prasanna
METAL: Caching Multi-level Indexes in Domain-Specific Architectures. ASPLOS (2) 2024: 715-729 - [c38]Milad Hakimi, Arrvindh Shriraman:
TapeFlow: Streaming Gradient Tapes in Automatic Differentiation. CGO 2024: 81-92 - 2022
- [c37]Parmida Vahdatniya, Amirali Sharifian, Reza Hojabr, Arrvindh Shriraman:
mu-grind: A Framework for Dynamically Instrumenting HLS-Generated RTL. PACT 2022: 346-358 - [c36]Ali Sedaghati, Milad Hakimi, Reza Hojabr, Arrvindh Shriraman:
X-cache: a modular architecture for domain-specific caches. ISCA 2022: 396-409 - [i2]Minh Bui, George Giovanis, Mo Chen, Arrvindh Shriraman:
OptimizedDP: An Efficient, User-friendly Library For Optimal Control and Dynamic Programming. CoRR abs/2204.05520 (2022) - 2021
- [c35]Naveen Vedula, Reza Hojabr, Ahmad Khonsari, Arrvindh Shriraman:
X-Layer: Building Composable Pipelined Dataflows for Low-Rank Convolutions. PACT 2021: 103-115 - [c34]Reza Hojabr, Ali Sedaghati, Amirali Sharifian, Ahmad Khonsari, Arrvindh Shriraman:
SPAGHETTI: Streaming Accelerators for Highly Sparse GEMM on FPGAs. HPCA 2021: 84-96 - [c33]Minh Bui, Michael Lu, Reza Hojabr, Mo Chen, Arrvindh Shriraman:
Real-Time Hamilton-Jacobi Reachability Analysis of Autonomous System With An FPGA. IROS 2021: 1666-1673 - 2020
- [c32]Seth Siriya, Minh Bui, Arrvindh Shriraman, Mo Chen, Ye Pu:
Safety-Guaranteed Real-Time Trajectory Planning for Underwater Vehicles in Plane-Progressive Waves. CDC 2020: 5249-5254 - [i1]Minh Bui, Michael Lu, Reza Hojabr, Mo Chen, Arrvindh Shriraman:
Real-Time Formal Verification of Autonomous Systems With An FPGA. CoRR abs/2012.04011 (2020)
2010 – 2019
- 2019
- [c31]Apala Guha, Naveen Vedula, Arrvindh Shriraman:
Deepframe: A Profile-Driven Compiler for Spatial Hardware Accelerators. PACT 2019: 68-81 - [c30]Amirali Sharifian, Reza Hojabr, Navid Rahimi, Sihao Liu
μIR -An intermediate representation for transforming and optimizing the microarchitecture of application accelerators. MICRO 2019: 940-953 - 2018
- [c29]Naveen Vedula, Arrvindh Shriraman, Snehasish Kumar, William N. Sumner
NACHOS: Software-Driven Hardware-Assisted Memory Disambiguation for Accelerators. HPCA 2018: 710-723 - [c28]Steve Margerm, Amirali Sharifian, Apala Guha, Arrvindh Shriraman, Gilles Pokam:
TAPAS: Generating Parallel Accelerators from Parallel Programs. MICRO 2018: 245-257 - [c27]Chen Song, Jiacheng Chen, Ryan Shea, Andy Sun, Arrvindh Shriraman, Jiangchuan Liu:
Scalable distributed visual computing for line-rate video streams. MMSys 2018: 186-194 - 2017
- [c26]Snehasish Kumar, Nick Sumner
Needle: Leveraging Program Analysis to Analyze and Extract Accelerators from Whole Programs. HPCA 2017: 565-576 - 2016
- [c25]Heng Liu, Arrvindh Shriraman, Evgenia Ternovska:
How to Speed Up CUDA-WSat-PcL by 5x. CANDAR 2016: 462-468 - [c24]Snehasish Kumar, Vijayalakshmi Srinivasan, Amirali Sharifian, Nick Sumner
Peruse and Profit: Estimating the Accelerability of Loops. ICS 2016: 21:1-21:13 - [c23]Snehasish Kumar, William N. Sumner
SPEC-AX and PARSEC-AX: extracting accelerator benchmarks from microprocessor benchmarks. IISWC 2016: 117-127 - [c22]Amirali Sharifian, Snehasish Kumar, Apala Guha, Arrvindh Shriraman:
Chainsaw: Von-neumann accelerators to leverage fused instruction chains. MICRO 2016: 49:1-49:14 - 2015
- [c21]Snehasish Kumar, Naveen Vedula, Arrvindh Shriraman, Vijayalakshmi Srinivasan:
DASX: Hardware Accelerator for Software Data Structures. ICS 2015: 361-372 - [c20]Snehasish Kumar, Arrvindh Shriraman, Naveen Vedula:
Fusion: design tradeoffs in coherent cache hierarchies for accelerators. ISCA 2015: 733-745 - 2014
- [j6]Inderpreet Singh, Arrvindh Shriraman, Wilson W. L. Fung, Mike O'Connor
Cache Coherence for GPU Architectures. IEEE Micro 34(3): 69-79 (2014) - [c19]Robert D. Cameron, Thomas C. Shermer, Arrvindh Shriraman, Kenneth S. Herdy, Dan Lin, Benjamin R. Hull, Meng Lin:
Bitwise data parallelism in regular expression matching. PACT 2014: 139-150 - [c18]Snehasish Kumar, Arrvindh Shriraman, Vijayalakshmi Srinivasan, Dan Lin, Jordon Phillips:
SQRL: hardware accelerator for collecting software data structures. PACT 2014: 475-476 - 2013
- [j5]Arrvindh Shriraman, Hongzhou Zhao, Sandhya Dwarkadas
An Application-Tailored Approach to Hardware Cache Coherence. Computer 46(10): 40-47 (2013) - [c17]Kai Shen, Arrvindh Shriraman, Sandhya Dwarkadas
Power containers: an OS facility for fine-grained power and energy management on multicore servers. ASPLOS 2013: 65-76 - [c16]Parosh Aziz Abdulla, Sandhya Dwarkadas, Ahmed Rezine, Arrvindh Shriraman, Yunyun Zhu:
Verifying safety and liveness for the FlexTM hybrid transactional memory. DATE 2013: 785-790 - [c15]Inderpreet Singh, Arrvindh Shriraman, Wilson W. L. Fung, Mike O'Connor
Cache coherence for GPU architectures. HPCA 2013: 578-590 - [c14]Hongzhou Zhao, Arrvindh Shriraman, Snehasish Kumar, Sandhya Dwarkadas:
Protozoa: adaptive granularity cache coherence. ISCA 2013: 547-558 - 2012
- [c13]Dan Lin, Nigel Medforth, Kenneth S. Herdy, Arrvindh Shriraman, Robert D. Cameron:
Parabix: Boosting the efficiency of text processing on commodity processors. HPCA 2012: 373-384 - [c12]Snehasish Kumar, Hongzhou Zhao, Arrvindh Shriraman, Eric Matthews, Sandhya Dwarkadas
Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy. MICRO 2012: 376-388 - [c11]Kai Shen, Arrvindh Shriraman, Sandhya Dwarkadas
Power and energy containers for multicore servers. SIGMETRICS 2012: 403-404 - 2011
- [j4]Arrvindh Shriraman, Sandhya Dwarkadas
Analyzing Conflicts in Hardware-Supported Memory Transactions. Int. J. Parallel Program. 39(1): 33-61 (2011) - [c10]Hongzhou Zhao, Arrvindh Shriraman, Sandhya Dwarkadas
SPATL: Honey, I Shrunk the Coherence Directory. PACT 2011: 33-44 - 2010
- [j3]Arrvindh Shriraman, Sandhya Dwarkadas
Implementation tradeoffs in the design of flexible transactional memory support. J. Parallel Distributed Comput. 70(10): 1068-1084 (2010) - [c9]Hongzhou Zhao, Arrvindh Shriraman, Sandhya Dwarkadas
SPACE: sharing pattern-based directory coherence for multicore scalability. PACT 2010: 135-146 - [c8]Arrvindh Shriraman, Sandhya Dwarkadas
Sentry: light-weight auxiliary memory access control. ISCA 2010: 407-418
2000 – 2009
- 2009
- [j2]Arrvindh Shriraman, Sandhya Dwarkadas, Michael L. Scott:
Tapping into Parallelism with Transactional Memory. login Usenix Mag. 34(2) (2009) - [c7]Arrvindh Shriraman, Sandhya Dwarkadas
Refereeing conflicts in hardware transactional memory. ICS 2009: 136-146 - 2008
- [c6]Arrvindh Shriraman, Sandhya Dwarkadas
Flexible Decoupled Transactional Memory Support. ISCA 2008: 139-150 - 2007
- [c5]Arrvindh Shriraman, Michael F. Spear
An integrated hardware-software approach to flexible transactional memory. ISCA 2007: 104-115 - [c4]Michael F. Spear
Alert-on-update: a communication aid for shared memory multiprocessors. PPoPP 2007: 132-133 - [c3]Michael F. Spear
Nonblocking transactions without indirection using alert-on-update. SPAA 2007: 210-220 - 2006
- [c2]Arrvindh Shriraman, Nagarajan Venkateswaran, Niranjan Soundararajan:
PASCOM: Power Model for Supercomputers. ARCS 2006: 326-340 - 2005
- [c1]Nagarajan Venkateswaran, Arrvindh Shriraman, Niranjan Soundararajan:
Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance. IPDPS 2005 - 2004
- [j1]Nagarajan Venkateswaran, Aditya Krishnan, S. Niranjan Kumar, Arrvindh Shriraman, Srinivas Sridharan:
Memory in processor: a novel design paradigm for supercomputing architectures. SIGARCH Comput. Archit. News 32(3): 19-26 (2004)
Coauthor Index
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