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Masaharu Tanaka
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2010 – 2019
- 2018
- [c6]Renya Yamamoto, Masaharu Tanaka, Haruhi Eto, Fujio Kurokawa:
A Study of FPGA Instance Based PLC Architecture Design and Automatic Generation Algorithm of Logic Code. CISIS 2018: 527-537 - 2017
- [c5]Masaharu Tanaka, Haruhi Eto, Nobumasa Matsui, Fujio Kurokawa:
An FPGA Based Heterogeneous Redundant Control System Using Controller Virtualization. CISIS 2017: 439-450 - 2016
- [c4]Yudai Shirakura, Taisei Segawa, Yuichiro Shibata, Kenichi Morimoto, Masaharu Tanaka, Masanori Nobe, Hidenori Maruta, Fujio Kurokawa:
A Redundant Design Approach with Diversity of FPGA Resource Mapping. ARC 2016: 119-131
2000 – 2009
- 2004
- [j2]Masaharu Tanaka, Masanobu Mizoguchi, Toshiaki Tange, Isao Takami, Shinji Suzuki:
Multiroute planning for aircraft using genetic algorithms. Syst. Comput. Jpn. 35(2): 39-48 (2004)
1990 – 1999
- 1998
- [c3]Mehrdad Salami, Hidenori Sakanashi, Masaharu Tanaka, Masaya Iwata, Takio Kurita, Tetsuya Higuchi:
On-Line Compression of High Precision Printer Images by Evolvable Hardware. Data Compression Conference 1998: 219-228 - [c2]Masaharu Tanaka, Hidenori Sakanashi, Mehrdad Salami, Masaya Iwata, Takio Kurita, Tetsuya Higuchi:
Data Compression for Digital Color Electrophotographic Printer with Evolvable Hardware. ICES 1998: 106-114 - 1995
- [j1]Eiji Fujiwara, Masaharu Tanaka:
Defect-Tolerant WSI File Memory System Using Address Permutation for Spare Allocation. IEICE Trans. Inf. Syst. 78-D(2): 130-137 (1995) - 1993
- [c1]Eiji Fujiwara, Masaharu Tanaka:
A Defect-Tolerant WSI File Memory System Using Address Permutation Scheme for Spare Allocation. DFT 1993: 183-190
Coauthor Index
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