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Hui Guo 0001
Person information
- affiliation: University of New South Wales, Sydney, NSW, Australia
Other persons with the same name
- Hui Guo — disambiguation page
- Hui Guo 0002
— East Carolina University, Greenville, North Carolina, USA
- Hui Guo 0003 — China University of Petroleum, Beijing, China (and 2 more)
- Hui Guo 0004
- Hui Guo 0005
- Hui Guo 0006 — Hohai University, Changzhou, China
- Hui Guo 0007 — UC Davis, CA, USA (and 1 more)
- Hui Guo 0008
- Hui Guo 0009
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2020 – today
- 2024
- [j14]Sajid Hussain
MP-ORAM: A Novel ORAM Design for Multicore Processor Systems. IEEE Trans. Dependable Secur. Comput. 21(4): 3719-3733 (2024) - 2021
- [j13]Sajid Hussain
COPS: A complete oblivious processing system. Microprocess. Microsystems 85: 104295 (2021)
2010 – 2019
- 2019
- [j12]Hui Yan, Xiaomin Zhu
DEFT: Dynamic Fault-Tolerant Elastic scheduling for tasks with uncertain runtime in cloud. Inf. Sci. 477: 30-46 (2019) - 2018
- [j11]Guipeng Liu, Xiaomin Zhu, Ji Wang, Deke Guo, Weidong Bao, Hui Guo:
SP-Partitioner: A novel partition method to handle intermediate data skew in spark streaming. Future Gener. Comput. Syst. 86: 1054-1063 (2018) - [c23]Mubashir Hussain
EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-Chip. ISVLSI 2018: 345-350 - [c22]Mubashir Hussain
A Bandwidth-Aware Authentication Scheme for Packet-Integrity Attack Detection on Trojan Infected NoC. VLSI-SoC 2018: 201-206 - 2017
- [j10]Tao Liu, Hui Guo, Sri Parameswaran
iCETD: An improved tag generation design for memory data authentication in embedded processor systems. Integr. 56: 96-104 (2017) - [c21]Mubashir Hussain
Packet Leak Detection on Hardware-Trojan Infected NoCs for MPSoC Systems. ICCSP 2017: 85-90 - 2016
- [j9]Xiaomin Zhu
Fault-Tolerant Scheduling for Real-Time Scientific Workflows with Elastic Resource Provisioning in Virtualized Clouds. IEEE Trans. Parallel Distributed Syst. 27(12): 3501-3517 (2016) - [c20]Tao Liu, Hui Guo, Sri Parameswaran
Improving tag generation for memory data authentication in embedded processor systems. ASP-DAC 2016: 50-55 - [c19]Mahanama Wickramasinghe
Data-Space Relocation to Improve Data Cache Performance for Embedded Multi-threaded Processor Systems. ICNCC 2016: 193-197 - [c18]Huangke Chen
EONS: Minimizing Energy Consumption for Executing Real-Time Workflows in Virtualized Cloud Data Centers. ICPP Workshops 2016: 385-392 - 2015
- [j8]Huangke Chen
Towards energy-efficient scheduling for real-time tasks under uncertain cloud computing environment. J. Syst. Softw. 99: 20-35 (2015) - [c17]Mahanama Wickramasinghe
Effective hardware-level thread synchronization for high performance and power efficiency in application specific multi-threaded embedded processors. ICCD 2015: 311-318 - 2014
- [c16]Mahanama Wickramasinghe
Energy-Aware Thread Scheduling for Embedded Multi-threaded Processors: Architectural Level Design and Implementation. ISVLSI 2014: 178-183 - 2013
- [j7]Ji Gu, Hui Guo, Tohru Ishihara
DLIC: Decoded loop instructions caching for energy-aware embedded processors. ACM Trans. Embed. Comput. Syst. 13(1): 6:1-6:26 (2013) - [c15]Mei Hong, Hui Guo, Sri Parameswaran
Dynamic encryption key design and management for memory data encryption in embedded systems. ISVLSI 2013: 70-75 - 2012
- [j6]Chuan He, Xiaomin Zhu, Hui Guo, Dishan Qiu, Jianqing Jiang:
Rolling-horizon scheduling for energy constrained distributed real-time embedded systems. J. Syst. Softw. 85(4): 780-794 (2012) - [c14]Mei Hong, Hui Guo, Xiaobo Sharon Hu
A cost-effective tag design for memory data authentication in embedded systems. CASES 2012: 17-26 - 2011
- [j5]Ji Gu, Hui Guo:
Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor Systems. Int. J. Handheld Comput. Res. 2(4): 42-58 (2011) - [j4]Ji Gu, Hui Guo, Patrick Li:
An on-chip instruction cache design with one-bit tag for low-power embedded systems. Microprocess. Microsystems 35(4): 382-391 (2011) - 2010
- [j3]Hui Guo, Sri Parameswaran
Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems. J. Syst. Archit. 56(4-6): 180-190 (2010) - [c13]Ji Gu, Hui Guo:
Enabling large decoded instruction loop caching for energy-aware embedded processors. CASES 2010: 247-256 - [c12]Mei Hong, Hui Guo:
FEDTIC: A Security Design for Embedded Systems with Insecure External Memory. FGIT 2010: 365-375 - [c11]Ji Gu, Hui Guo:
An Energy Efficient Instruction Prefetching Scheme for Embedded Processors. UCMA 2010: 73-88
2000 – 2009
- 2009
- [j2]Ji Gu, Hui Guo:
An Efficient Segmental Bus-Invert Coding Method for Instruction Memory Data Bus Switching Reduction. EURASIP J. Embed. Syst. 2009 (2009) - [j1]Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors. IET Comput. Digit. Tech. 3(1): 94-108 (2009) - [c10]Ji Gu, Hui Guo:
A Segmental Bus-invert Coding Method for Instruction Memory Data Bus Power Efficiency. ISCAS 2009: 137-140 - [c9]Ji Gu, Hui Guo, Patrick Li:
ROBTIC: An On-chip Instruction Cache Design for Low Power Embedded Systems. RTCSA 2009: 419-424 - 2008
- [c8]Mei Hong, Hui Guo, Bin Luo
Security Design for Multi-service Smart Card Systems. FGCN (1) 2008: 299-304 - 2006
- [c7]Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
Application specific forwarding network and instruction encoding for multi-pipe ASIPs. CODES+ISSS 2006: 241-246 - [c6]Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
Customization of application specific heterogeneous multi-pipeline processors. DATE 2006: 746-751 - 2005
- [c5]Hui Guo, Sri Parameswaran
Balancing System Level Pipelines with Stage Voltage Scaling. ISVLSI 2005: 287-289 - 2004
- [c4]Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
Dual-pipeline heterogeneous ASIP design. CODES+ISSS 2004: 12-17
1990 – 1999
- 1998
- [c3]Hui Guo, Sri Parameswaran:
Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines. ASP-DAC 1998: 99-104 - [c2]Sri Parameswaran, Hui Guo:
Power Reduction in Pipelines. ASP-DAC 1998: 545-550 - 1997
- [c1]Sri Parameswaran, Hui Guo:
Power consumption in CMOS combinational logic blocks at high frequencies. ASP-DAC 1997: 195-200
Coauthor Index
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last updated on 2024-12-10 21:41 CET by the dblp team
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