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Mu-Chen Huang

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2010 – 2019

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2017
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  - conf/isscc/LiuH17
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Chun-Cheng Liu, Mu-Chen Huang:
28.1 A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter. ISSCC 2017: 466-467
2016
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Chun-Cheng Liu, Mu-Chen Huang, Yu-Hsuan Tu:
A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC. IEEE J. Solid State Circuits 51(12): 2941-2950 (2016)
2011
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Chen-Yen Ho, Zwei-Mei Lee, Mu-Chen Huang, Sheng-Jui Huang:
A 75.1dB SNDR, 80.2dB DR, 4th-order feed-forward continuous-time sigma-delta modulator with hybrid integrator for silicon TV-tuner application. A-SSCC 2011: 261-264
2010
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Mu-Chen Huang, Shen-Iuan Liu:
A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive Biasing. IEEE Trans. Circuits Syst. II Express Briefs 57-II(1): 11-15 (2010)

2000 – 2009

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2009
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Mu-Chen Huang, Shen-Iuan Liu:
A Fully Differential Comparator-Based Switched-Capacitor DeltaSigma Modulator. IEEE Trans. Circuits Syst. II Express Briefs 56-II(5): 369-373 (2009)

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