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Yen-Jen Chang
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2020 – today
- 2024
- [j24]Yen-Jen Chang
, Yi-Da Wu, Yu-Lin Liao, Chien-Ho Wang, Yen-Ching Wu:
Modified YOLO network model for metaphase cell detection in antinuclear antibody images. Eng. Appl. Artif. Intell. 127(Part B): 107392 (2024) - [j23]Yen-Jen Chang, Kun-Lin Tsai, Wei-Cheng Jiang
Content-aware malicious webpage detection using convolutional neural network. Multim. Tools Appl. 83(3): 8145-8163 (2024) - [j22]Yen-Jen Chang
Target-Aware Yield Prediction (TAYP) Model Used to Improve Agriculture Crop Productivity. IEEE Trans. Geosci. Remote. Sens. 62: 1-11 (2024) - 2023
- [j21]Yen-Jen Chang
Multi-Logic Sense Amplifier (MLSA) Design for In-Memory Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 371-381 (2023) - 2021
- [j20]Kun-Lin Tsai
Accuracy-Configurable Radix-4 Adder With a Dynamic Output Modification Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 68(8): 3328-3336 (2021) - [j19]Yen-Jen Chang
Data Retention-Based Low Leakage Power TCAM for Network Packet Routing. IEEE Trans. Circuits Syst. II Express Briefs 68(2): 757-761 (2021) - 2020
- [j18]Yen-Jen Chang, Yu-Cheng Cheng
A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism. IEEE Access 8: 114842-114853 (2020) - [j17]Yen-Jen Chang, Kun-Lin Tsai
Low-power ternary content-addressable memory design based on a voltage self-controlled fin field-effect transistor segment. Comput. Electr. Eng. 81: 106528 (2020)
2010 – 2019
- 2019
- [j16]Yen-Jen Chang, Yu-Cheng Cheng
Imprecise 4-2 compressor design used in image processing applications. IET Circuits Devices Syst. 13(6): 848-856 (2019) - 2017
- [c18]Chun-Hsiang Lai, Yu-Cheng Cheng, Tung-Chi Wu, Yen-Jen Chang:
Radix-4 adder design with refined carry. DSC 2017: 300-304 - 2016
- [c17]Yu-Cheng Cheng, Jin-Hao Chen, Tung-Chi Wu, Yen-Jen Chang:
Low leakage mask vertical control TCAM for network router. APCCAS 2016: 469-472 - 2015
- [j15]Yen-Jen Chang, Tung-Chi Wu:
Master-Slave Match Line Design for Low-Power Content-Addressable Memory. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1740-1749 (2015) - 2014
- [j14]Kun-Lin Tsai
Automatic Charge Balancing Content Addressable Memory With Self-control Mechanism. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(10): 2834-2841 (2014) - 2013
- [j13]Yen-Jen Chang, Kun-Lin Tsai
Low Leakage TCAM for IP Lookup Using Two-Side Self-Gating. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(6): 1478-1486 (2013) - [j12]Yen-Jen Chang, Hsiang-Yu Lu:
Improving the performance of port range check for network packet filtering. ACM Trans. Design Autom. Electr. Syst. 19(1): 3:1-3:21 (2013) - [c16]Ya-Chun Lin, Yen-Jen Chang, Tung-Chi Wu:
Low-power content-addressable memory design using a double match-line (DML) architecture. MWSCAS 2013: 425-428 - 2011
- [j11]Chuen-Horng Lin, Der-Chen Huang, Yung-Kuan Chan
Fast color-spatial feature based image retrieval methods. Expert Syst. Appl. 38(9): 11412-11420 (2011) - [c15]Yen-Jen Chang, Tung-Chi Wu:
A low-power TCAM design using mask-aware match-line (MAML) technique. ACM Great Lakes Symposium on VLSI 2011: 109-114 - 2010
- [j10]Yen-Jen Chang:
Using the Dynamic Power Source Technique to Reduce TCAM Leakage Power. IEEE Trans. Circuits Syst. II Express Briefs 57-II(11): 888-892 (2010) - [j9]Yen-Jen Chang:
Don't-Care Gating (DCG) TCAM Design Used in Network Routing Table. IEEE Trans. Very Large Scale Integr. Syst. 18(11): 1599-1607 (2010)
2000 – 2009
- 2009
- [j8]Yen-Jen Chang:
A High-Performance and Energy-Efficient TCAM Design for IP-Address Lookup. IEEE Trans. Circuits Syst. II Express Briefs 56-II(6): 479-483 (2009) - [c14]Yung-Feng Cheng, Yen-Jen Chang:
A Novel High Performance Ternary CAM (TCAM) for LPM. ESA 2009: 22-27 - [c13]Jin-Wei Yang, Yen-Jen Chang:
Low Power Selected Gating Frame Buffer (SGFB) Design. ESA 2009: 140-145 - 2008
- [j7]Yen-Jen Chang, Yuan-Hong Liao:
Hybrid-Type CAM Design for Both Power and Performance Efficiency. IEEE Trans. Very Large Scale Integr. Syst. 16(8): 965-974 (2008) - [c12]Yen-Jen Chang:
Exploiting frequent opcode locality for power efficient instruction cache. ACM Great Lakes Symposium on VLSI 2008: 399-402 - 2007
- [j6]Yen-Jen Chang, Maofeng Lan:
Two New Techniques Integrated for Energy-Efficient TLB Design. IEEE Trans. Very Large Scale Integr. Syst. 15(1): 13-23 (2007) - [c11]Yen-Jen Chang, Yuan-Hong Liao, Shanq-Jang Ruan:
Improve CAM power efficiency using decoupled match line scheme. DATE 2007: 165-170 - 2006
- [j5]Yen-Jen Chang:
An Energy-Efficient BTB Lookup Scheme for Embedded Processors. IEEE Trans. Circuits Syst. II Express Briefs 53-II(9): 817-821 (2006) - [c10]Yen-Jen Chang:
Lazy BTB: reduce BTB energy consumption using dynamic profiling. ASP-DAC 2006: 917-922 - [c9]Yen-Jen Chang:
An ultra low-power TLB design. DATE 2006: 1122-1127 - [c8]Yen-Jen Chang:
An Alternative Real-Time Filter Scheme to Block Buffering. VLSI Design 2006: 762-765 - 2005
- [j4]Yen-Jen Chang, Feipei Lai:
Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories. IEEE Micro 25(4): 20-32 (2005) - 2004
- [j3]Yen-Jen Chang, Feipei Lai, Chia-Lin Yang
Zero-aware asymmetric SRAM cell for reducing cache power in writing zero. IEEE Trans. Very Large Scale Integr. Syst. 12(8): 827-836 (2004) - [c7]Yen-Jen Chang, Chia-Lin Yang
Value-Conscious Cache: Simple Technique for Reducing Cache Access Power. DATE 2004: 16-21 - [c6]Yen-Jen Chang, Yung-Ching Weng, Feipei Lai:
Enhanced object management for high performance web proxies. SAC 2004: 1711-1716 - 2003
- [j2]Yen-Jen Chang, Shanq-Jang Ruan, Feipei Lai:
Design and analysis of low-power cache using two-level filter scheme. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 568-580 (2003) - [c5]Yen-Jen Chang, Chia-Lin Yang, Feipei Lai:
A power-aware SWDR cell for reducing cache write power. ISLPED 2003: 14-17 - 2002
- [j1]Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Feipei Lai, Uwe Schwiegelshohn
ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 942-949 (2002) - [c4]Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Chia-Lin Ho, Feipei Lai:
Energy analysis of bipartition architecture for pipelined circuits. APCCAS (2) 2002: 7-11 - [c3]Yen-Jen Chang, Feipei Lai:
Paged cache: an efficient partition architecture for reducing power, area and access time. APCCAS (2) 2002: 473-478 - [c2]Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan:
Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost. ICCD 2002: 334-339 - [c1]Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan:
An Efficient Two-Level Filter Scheme for Low Power Cache. IWLS 2002: 61-66
Coauthor Index
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last updated on 2024-04-24 23:10 CEST by the dblp team
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