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Rafael Trapani Possignolo
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2020 – today
- 2020
- [j4]Sheng-Hong Wang, Rafael Trapani Possignolo, Haven Blake Skinner, Jose Renau
:
LiveHD: A Productive Live Hardware Development Flow. IEEE Micro 40(4): 67-75 (2020) - [c12]Haven Blake Skinner, Rafael Trapani Possignolo, Sheng-Hong Wang, Jose Renau:
LiveSim: A Fast Hot Reload Simulator for HDLs. ISPASS 2020: 126-135
2010 – 2019
- 2019
- [c11]Rafael Trapani Possignolo, Jose Renau
SMatch: Structural Matching for Fast Resynthesis in FPGAs. DAC 2019: 75 - [c10]Daphne I. Gorman, Rafael Trapani Possignolo, Jose Renau:
EMI Architectural Model and Core Hopping. MICRO 2019: 899-910 - 2018
- [b1]Rafael Trapani Possignolo:
Improving the Productivity of Hardware Design. University of California, Santa Cruz, USA, 2018 - [j3]Rafael Trapani Possignolo
GPU NTC Process Variation Compensation With Voltage Stacking. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1713-1726 (2018) - [p1]Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Blake Skinner, Jose Renau:
Automated Pipeline Transformations with Fluid Pipelines. Advanced Logic Synthesis 2018: 125-150 - 2017
- [c9]Rafael Trapani Possignolo, Jose Renau:
LiveSynth: Towards an Interactive Synthesis Flow. DAC 2017: 74:1-74:6 - [c8]Elnaz Ebrahimi, Rafael Trapani Possignolo, Jose Renau:
Level shifter design for voltage stacking. ISCAS 2017: 1-4 - [c7]Haven Blake Skinner, Rafael Trapani Possignolo, Jose Renau:
Liam: an actor based programming model for HDLs. MEMOCODE 2017: 185-188 - 2016
- [j2]Ehsan K. Ardestani, Rafael Trapani Possignolo, José Luis Briz
Managing Mismatches in Voltage Stacking with CoreUnfolding. ACM Trans. Archit. Code Optim. 12(4): 43:1-43:26 (2016) - [c6]Ilya Ganusov, Henri Fraisse, Aaron Ng, Rafael Trapani Possignolo, Sabya Das:
Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs. FPL 2016: 1-10 - [c5]Rafael Trapani Possignolo, Jose Renau:
LiveSynth: Towards an interactive synthesis flow. Hot Chips Symposium 2016: 1 - [c4]Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Blake Skinner, Jose Renau:
Fluid Pipelines: Elastic circuitry meets Out-of-Order execution. ICCD 2016: 233-240 - [c3]Elnaz Ebrahimi, Rafael Trapani Possignolo, Jose Renau:
SRAM voltage stacking. ISCAS 2016: 1634-1637 - 2015
- [j1]Rafael Trapani Possignolo, Cíntia Borges Margi
Quantum-assisted QD-CFS signatures. J. Comput. Syst. Sci. 81(2): 458-467 (2015) - 2012
- [c2]Rafael Trapani Possignolo, Cíntia B. Margi
A Quantum-classical Hybrid Architecture for Security Algorithms Acceleration. TrustCom 2012: 1032-1037
2000 – 2009
- 2009
- [c1]Rafael Trapani Possignolo, Omar Hammami:
Optimized joint NARX ANN - embedded processor design methodology. ICECS 2009: 499-502
Coauthor Index
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