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Koki Okabe
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2000 – 2009
- 2009
- [c6]Yoshiei Sato, Ryu-ichi Nagaoka, Akihiro Musa, Ryusuke Egawa, Hiroyuki Takizawa
, Koki Okabe, Hiroaki Kobayashi:
Performance tuning and analysis of future vector processors based on the roofline model. MEDEA@PACT 2009: 7-14 - [c5]Takashi Soga, Akihiro Musa, Youichi Shimomura, Ryusuke Egawa, Ken'ichi Itakura, Hiroyuki Takizawa
Performance evaluation of NEC SX-9 using real science and engineering applications. SC 2009 - 2008
- [c4]Akihiro Musa, Yoshiei Sato, Takashi Soga, Ryusuke Egawa, Hiroyuki Takizawa
Effects of MSHR and Prefetch Mechanisms on an On-Chip Cache of the Vector Architecture. ISPA 2008: 335-342 - [c3]Akihiro Musa, Yoshiei Sato, Takashi Soga, Koki Okabe, Ryusuke Egawa, Hiroyuki Takizawa
A shared cache for a chip multi vector processor. MEDEA@PACT 2008: 24-29 - [p1]Hiroaki Kobayashi, Ryusuke Egawa, Hiroyuki Takizawa, Koki Okabe, Akihiko Musa, Takashi Soga, Yoichi Shimomura:
First Experiences with NEC SX-9. High Performance Computing on Vector Systems 2008: 3-11 - 2007
- [c2]Akihiro Musa, Yoshiei Sato, Ryusuke Egawa, Hiroyuki Takizawa
An on-chip cache design for vector processors. MEDEA@PACT 2007: 17-23 - 2006
- [c1]Akihiro Musa, Hiroyuki Takizawa
Implications of Memory Performance for Highly Efficient Supercomputing of Scientific Applications. ISPA 2006: 845-858
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