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Carl J. Anderson
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2000 – 2009
- 2009
- [c3]Carl J. Anderson:
Beyond innovation: dealing with the risks and complexity of processor design in 22nm. DAC 2009: 103 - [c2]Carl J. Anderson:
One look into the future of CMOS chip design. ISPD 2009: 1-2 - 2002
- [j5]James D. Warnock, John M. Keaty, John G. Petrovick, Joachim G. Clabes, Charles J. Kircher, Byron Krauter, Phillip J. Restle, Brian A. Zoric, Carl J. Anderson:
The circuit and physical design of the POWER4 microprocessor. IBM J. Res. Dev. 46(1): 27-52 (2002)
1990 – 1999
- 1998
- [j4]Ching-Te Chuang, Pong-Fei Lu, Carl J. Anderson:
SOI for digital CMOS VLSI: design considerations and advances. Proc. IEEE 86(4): 689-720 (1998) - 1997
- [j3]Pong-Fei Lu, Ching-Te Chuang, Jin Ji, Lawrence F. Wagner, Chang-Ming Hsieh, Jente B. Kuang, Louis Lu-Chen Hsu, Mario M. Pelella Jr., Shao-Fu Sanford Chu, Carl J. Anderson:
Floating-body effects in partially depleted SOI CMOS circuits. IEEE J. Solid State Circuits 32(8): 1241-1253 (1997) - [j2]Charles F. Webb, Carl J. Anderson, Leon J. Sigal, Kenneth L. Shepard, John S. Liptay, James D. Warnock, Brian W. Curran, Barry Krumm, Mark D. Mayo, Peter J. Camporese, Eric M. Schwarz, Mark S. Farrell, Phillip J. Restle, Robert M. Averill III, Timothy J. Slegel, William V. Huott, Yuen H. Chan, Bruce Wile, Thao N. Nguyen, Philip G. Emma, Daniel K. Beece, Ching-Te Chuang, Cyril Price:
A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders. IEEE J. Solid State Circuits 32(11): 1676-1682 (1997) - 1996
- [c1]Pong-Fei Lu, Jin Ji, Ching-Te Chuang, Lawrence F. Wagner, Chang-Ming Hsieh, Jente Benedict Kuang, L. Hsu, Mario M. Pelella Jr., Shao-Fu Sanford Chu, Carl J. Anderson:
Floating body effects in partially-depleted SOI CMOS circuits. ISLPED 1996: 139-144 - 1995
- [j1]Ghavam G. Shahidi, James D. Warnock, James Comfort, Stephen E. Fischer, Patricia A. McFarland, Alexandre Acovic, Terry I. Chappell, Barbara A. Chappell, Tak H. Ning, Carl J. Anderson, Robert H. Dennard, Jack Y.-C. Sun, Michael R. Polcari, Bijan Davari:
CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications. IBM J. Res. Dev. 39(1-2): 229-244 (1995)
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