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Suman Sau
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2020 – today
- 2021
- [j3]Rourab Paul
, Nimisha Ghosh
Blockchain based secure smart city architecture using low resource IoTs. Comput. Networks 196: 108234 (2021) - [i9]Rourab Paul, Sreetama Sarkar, Suman Sau, Koushik Chakraborty, Sanghamitra Roy, Amlan Chakrabarti:
Voltage Scaling for Partitioned Systolic Array in A Reconfigurable Platform. CoRR abs/2102.06888 (2021)
2010 – 2019
- 2019
- [i8]Rourab Paul, Nimisha Ghosh
IoT based Smart Access Controlled Secure Smart City Architecture Using Blockchain. CoRR abs/1908.11538 (2019) - 2018
- [c6]Ming Ming Wong, Jawad Haj-Yahya, Suman Sau, Anupam Chattopadhyay:
A New High Throughput and Area Efficient SHA-3 Implementation. ISCAS 2018: 1-5 - 2017
- [j2]Swagata Mandal, Rourab Paul
Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware. Microprocess. Microsystems 51: 313-330 (2017) - [c5]Suman Sau, Jawad Haj-Yahya, Ming Ming Wong, Kwok-Yan Lam
Survey of secure processors. SAMOS 2017: 253-260 - 2016
- [j1]Swagata Mandal
A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code. IEEE Embed. Syst. Lett. 8(4): 65-68 (2016) - 2015
- [c4]Swagata Mandal, Suman Sau, Amlan Chakrabarti
FPGA Implementation of High Speed Latency Optimized Optical Communication System Based on Orthogonal Concatenated Code. ATS 2015: 169-174 - [c3]Swagata Mandal, Suman Sau, Amlan Chakrabarti
FPGA Based Novel High Speed DAQ System Design with Error Correction. ISVLSI 2015: 80-85 - [i7]Swagata Mandal, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay:
FPGA based High Speed Data Acquisition System for High Energy Physics Application. CoRR abs/1503.08819 (2015) - [i6]Suman Sau, Swagata Mandal, Jogender Saini, Amlan Chakrabarti, Subhasis Chattopadhyay:
High speed fault tolerant secure communication for muon chamber using fpga based gbt emulator. CoRR abs/1505.04569 (2015) - [i5]Swagata Mandal, Suman Sau, Amlan Chakrabarti, Jogendra Saini, Sushanta Kumar Pal, Subhasish Chattopadhyay:
FPGA based Novel High Speed DAQ System Design with Error Correction. CoRR abs/1507.01777 (2015) - [i4]Swagata Mandal, Rourab Paul, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay:
A Novel Method for Soft Error Mitigation in FPGA using Adaptive Cross Parity Code. CoRR abs/1509.06891 (2015) - 2012
- [c2]Suman Sau, Rourab Paul
A novel AES-256 implementation on FPGA using co-processor based architecture. ICACCI 2012: 632-638 - [i3]Rourab Paul, Sangeet Saha, Suman Sau, Amlan Chakrabarti:
Design and implementation of real time AES-128 on real time operating system for multiple FPGA communication. CoRR abs/1205.2153 (2012) - [i2]Rourab Paul, Suman Sau, Amlan Chakrabarti:
Architecture for real time continuous sorting on large width data volume for fpga based applications. CoRR abs/1206.1567 (2012) - [i1]Sangeet Saha, Chandrajit Pal, Rourab Paul, Satyabrata Maity, Suman Sau:
A brief experience on journey through hardware developments for image processing and its applications on Cryptography. CoRR abs/1212.6303 (2012) - 2011
- [c1]Suman Sau, Chandrajit Pal
Design and implementation of real time secured RS232 link for multiple FPGA communication. ICCCS 2011: 391-396
Coauthor Index
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