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Chanjin Park
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2020 – today
- 2023
- [j4]Kyeong-Soo Kang
, Ji-Hwan Park
A New PWM Operational Scheme for MicroLED Displays Using Inverter and Dynamic SWEEP Signal Slope for Low Gray Level Expression. IEEE Access 11: 135915-135921 (2023) - [c5]Youngmin Jo, Anil Kavala, Tongsung Kim, Byung-Kwan Chun, Jungjune Park, Taesung Lee, Jungmin Seo, Manjae Yang, Taehyeon Park, Hyunjin Kwon, Cheolhui Lee, Younghoon Son, Junghwan Kwak, Younggyu Lee, Hwan-Seok Ku, Dae-Hoon Na, Changyeon Yu, Jonghoon Park, Jae-Hwan Kim, Hyojin Kwon, Chan-ho Kim, Moon-Ki Jung, Chanjin Park, Donghyun Seo, Moosung Kim, Seungjae Lee, Jin-Yub Lee, Dongku Kang, Chiweon Yoon, Sunghoi Hur:
A 3.0 Gb/s/pin 4th generation F-chip with Toggle 5.0 Specification for 16Tb NAND Flash Memory Multi chip Package. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j3]Chanjin Park, Wonhyuk Lee
A Study on Traffic Prediction for the Backbone of Korea's Research and Science Network Using Machine Learning. J. Web Eng. 21(5) (2022)
2010 – 2019
- 2017
- [c4]Chanjin Park, Wonhyuk Lee, Kuinam J. Kim, Hyuncheol Kim:
Research on Design of End Site Architecture to Connect LHCONE in KREONET. ICISA 2017: 745-750 - 2015
- [c3]Hyun-Jin Kim, Jeong-Don Lim, Jang-Woo Lee, Dae-Hoon Na
7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip. ISSCC 2015: 1-3
2000 – 2009
- 2007
- [j2]Yoohoon Kang, Chanjin Park, Chisu Wu:
Reverse-engineering 1-n associations from Java bytecode using alias analysis. Inf. Softw. Technol. 49(2): 81-98 (2007) - 2006
- [c2]Taeksu Kim, Chanjin Park, Chisu Wu:
Mock Object Models for Test Driven Development. SERA 2006: 221-228 - 2004
- [j1]Chanjin Park, Euyseok Hong, Chisu Wu:
A Method to Preserve Layered Architectural Style in Development Phases. IEICE Trans. Inf. Syst. 87-D(7): 1965-1970 (2004) - [c1]Chanjin Park, Yoohoon Kang, Chisu Wu, Kwangkeun Yi:
A Static Reference Flow Analysis to Understand Design Pattern Behavior. WCRE 2004: 300-301
Coauthor Index
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