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Arjan J. van Genderen
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2000 – 2009
- 2009
- [c9]Marius Enachescu, Sorin Cotofana, Arjan J. van Genderen, Dimitrios Tsamados, Adrian M. Ionescu:
Can SG-FET Replace FET in Sleep Mode Circuits? NanoNet 2009: 99-104 - 2007
- [e1]Koen Bertels, Walid A. Najjar, Arjan J. van Genderen, Stamatis Vassiliadis:
FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007. IEEE 2007, ISBN 1-4244-1060-6 [contents]
1990 – 1999
- 1996
- [c8]Arjan J. van Genderen, N. P. van der Meijs:
Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction. DAC 1996: 758-763 - [c7]Arjan J. van Genderen, N. P. van der Meijs, T. Smedes:
Fast Computation of Substrate Resistances in Large Circuits. ED&TC 1996: 560-565 - 1995
- [c6]N. P. van der Meijs, Arjan J. van Genderen:
Delayed Frontal Solution for Finite-Element Based Resistance Extraction. DAC 1995: 273-278 - [c5]Arjan J. van Genderen:
Network initialization in a switch-level simulator. ED&TC 1995: 596-597 - [c4]T. Smedes, N. P. van der Meijs, Arjan J. van Genderen:
Extraction of circuit models for substrate cross-talk. ICCAD 1995: 199-206 - [c3]Frederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs:
Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits. ICCD 1995: 360-365 - 1993
- [c2]Arjan J. van Genderen, N. P. van der Meijs:
Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures. ICCAD 1993: 764-769
1980 – 1989
- 1989
- [c1]N. P. van der Meijs, Arjan J. van Genderen:
An Efficient Finite Element Method for Submicron IC Capacitance Extraction. DAC 1989: 678-681
Coauthor Index
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