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Gabriel Caffarena
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2020 – today
- 2025
- [j15]Pablo Pérez-Tirador, Madhav P. Desai, Alejandro Rodriguez, Elena Berral, Teresa Romero, Gabriel Caffarena, Ruzica Jevtic:
Side-channel attacks and countermeasures for heart rate retrieval from ECG characterization device. Int. J. Inf. Sec. 24(1): 8 (2025) - 2022
- [j14]Abraham Otero
, Paulo Félix
A fault-tolerant clustering algorithm for processing data from multiple streams. Inf. Sci. 584: 649-664 (2022) - [c30]Ruzica Jevtic, Pablo Pérez-Tirador, Carmen Cabezaolias, Pablo Carnero, Gabriel Caffarena:
Side-channel Attack Countermeasure Based on Power Supply Modulation. EUSIPCO 2022: 618-622 - 2021
- [c29]Javier Hormigo, Gabriel Caffarena:
FPGA acceleration of bit-true simulations for word-length optimization. ARITH 2021: 119-122
2010 – 2019
- 2019
- [j13]Roberto Sierra, Carlos Carreras
Witelo: Automated generation and timing characterization of distributed-control macroblocks for high-performance FPGA designs. Integr. 68: 1-11 (2019) - [c28]Roberto Sierra, Filippo Mangani, Carlos Carreras
High-Performance Decoding of Variable-Length Memory Data Packets for FPGA Stream Processing. FPL 2019: 307-313 - 2018
- [c27]Roberto Sierra, Carlos Carreras
Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs. PATMOS 2018: 7-12 - 2016
- [j12]Gabriel Caffarena
Quantization Noise Power Estimation for Floating-Point DSP Circuits. IEEE Trans. Circuits Syst. II Express Briefs 63-II(6): 593-597 (2016) - [c26]Pablo Pérez-Tirador
Hardware Accelerator to Compute the Minimum Embedding Dimension of ECG Records. IWBBIO 2016: 254-265 - [c25]Kartik Lakhotia, Gabriel Caffarena
Low-Power, Low-Latency Hermite Polynomial Characterization of Heartbeats Using a Field-Programmable Gate Array. IWBBIO 2016: 266-276 - 2015
- [j11]Roberto Sierra, Carlos Carreras
A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(1): 52-62 (2015) - [c24]Ana Iriarte, Gabriel Caffarena
Iterative reconstruction for pet scanners with continuous scintillators. EMBC 2015: 2259-2262 - 2014
- [j10]Carlos Oscar Sánchez Sorzano
Comparing scientific performance among equals. Scientometrics 101(3): 1731-1745 (2014) - [c23]Pablo Calleja, Gabriel Caffarena
FPGA Design of Delay-Based Digital Effects for Electric Guitar. ARC 2014: 213-218 - [c22]Alberto Gil, Gabriel Caffarena, David G. Márquez, Abraham Otero:
Hermite Polynomial Characterization of Heartbeats with Graphics Processing Units. IWBBIO 2014: 527-538 - [c21]Carlos Oscar Sánchez Sorzano, Javier Vargas, José Miguel de la Rosa-Trevín, Airen Zaldívar-Peraza, Joaquín Otón, Vahid Abrishami, Ignacio Foche, Roberto Marabini, Gabriel Caffarena, José María Carazo:
Outlier detection for single particle analysis in Electron Microscopy. IWBBIO 2014: 950-959 - [c20]Eduardo Garcia de La Cueva, Miguel Mateo de La Puente, Alessandro Deideri, Ana Iriarte, Carlos Oscar Sánchez Sorzano, Gabriel Caffarena:
2D and 3D Alignment for Electron Microscopy via Graphics Processing Units. IWBBIO 2014: 960-971 - 2013
- [j9]Javier Hormigo
Self-Reconfigurable Constant Multiplier for FPGA. ACM Trans. Reconfigurable Technol. Syst. 6(3): 14:1-14:17 (2013) - [c19]Eduardo I. Boemo, Juan P. Oliver, Gabriel Caffarena
Tracking the pipelining-power rule along the FPGA technical literature. FPGAworld 2013: 9:1-9:5 - 2012
- [j8]Gabriel Caffarena
Quantization of VLSI digital signal processing systems. EURASIP J. Adv. Signal Process. 2012: 32 (2012) - [j7]Jean-Charles Naud, Daniel Ménard, Gabriel Caffarena
A Discrete Model for Correlation Between Quantization Noises. IEEE Trans. Circuits Syst. II Express Briefs 59-II(11): 800-804 (2012) - [c18]Gabriel Caffarena, Daniel Ménard:
Many-core parallelization of fixed-point optimization of VLSI circuits through GPU devices. DASIP 2012: 1-8 - [c17]Carlos Oscar Sánchez Sorzano, Joaquín Otón
Image processing for Cellular tomography using soft X-rays. ISBI 2012: 1322 - 2010
- [j6]Gabriel Caffarena
SQNR Estimation of Fixed-Point DSP Algorithms. EURASIP J. Adv. Signal Process. 2010 (2010) - [c16]Gabriel Caffarena, Juan A. López, Angel Fernandez Herrero, Carlos Carreras:
SQNR estimation of non-linear fixed-point algorithms. EUSIPCO 2010: 522-526 - [c15]Gabriel Caffarena, Carlos Carreras:
Precision-wise architectural synthesis of DSP circuits. EUSIPCO 2010: 562-566 - [c14]Gabriel Caffarena
Fast Fixed-Point Optimization of DSP Algorithms. VLSI-SoC (Selected Papers) 2010: 182-205 - [c13]Gabriel Caffarena
Fast fixed-point optimization of DSP algorithms. VLSI-SoC 2010: 195-200 - [c12]Gabriel Caffarena
Architectural synthesis of DSP circuits under simultaneous error and time constraints. VLSI-SoC 2010: 322-327
2000 – 2009
- 2009
- [j5]Gabriel Caffarena, Juan A. López
Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs. Int. J. Reconfigurable Comput. 2009: 703267:1-703267:14 (2009) - [c11]Slobodan Bojanic, Vukasin Pejovic, Gabriel Caffarena
Behavioural Biometrics Hardware Based on Bioinformatics Matching. CISIS 2009: 171-178 - 2008
- [j4]Juan A. López
Fast and accurate computation of the roundoff noise of linear time-invariant systems. IET Circuits Devices Syst. 2(4): 393-408 (2008) - [c10]Gabriel Caffarena
Optimized Architectural Synthesis of Fixed-Point Datapaths. ReConFig 2008: 85-90 - 2007
- [j3]Gabriel Caffarena
Fpga Acceleration for DNA Sequence Alignment. J. Circuits Syst. Comput. 16(2): 245-266 (2007) - [c9]Ruzica Jevtic
Switching Activity Models for Power Estimation in FPGA Multipliers. ARC 2007: 201-213 - 2006
- [j2]Slobodan Bojanic, Gabriel Caffarena
FPGA for pseudorandom generator cryptanalysis. Microprocess. Microsystems 30(2): 63-71 (2006) - [j1]Gabriel Caffarena
Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits. IEEE Trans. Circuits Syst. II Express Briefs 53-II(5): 339-343 (2006) - [c8]Gabriel Caffarena
High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs. FPL 2006: 1-4 - [c7]Angel Fernandez Herrero, Alberto Jimenez-Pacheco, Gabriel Caffarena
Design and Implementation of a Hardware Module for Equalisation in A 4G MIMO Receiver. FPL 2006: 1-4 - [c6]Gabriel Caffarena
Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA Resources. SoC 2006: 1-4 - 2004
- [c5]Juan A. López, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz:
Analysis of limit cycles by means of affine arithmetic computer-aided tests. EUSIPCO 2004: 991-994 - [c4]Gabriel Caffarena, Angel Fernández, Carlos Carreras, Octavio Nieto-Taladriz:
Fixed-point refinement of OFDM-based adaptive equalizers: An heuristic approach. EUSIPCO 2004: 1353-1356 - [c3]Gerardo Leyva, Gabriel Caffarena
A Generator of High-Speed Floating-Point Modules. FCCM 2004: 306-307 - [c2]Gabriel Caffarena, Slobodan Bojanic, Juan A. López, Carlos E. Pedreira, Octavio Nieto-Taladriz:
High-speed systolic array for gene matching. FPGA 2004: 248 - 2003
- [c1]Juan A. López
Fast characterization of the noise bounds derived from coefficient and signal quantization. ISCAS (4) 2003: 309-312
Coauthor Index
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