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Jing-Reng Huang
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2000 – 2009
- 2007
- [j3]Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu:
STEAC: A Platform for Automatic SOC Test Integration. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 541-545 (2007) - 2004
- [j2]Ming-Jun Hsiao, Jing-Reng Huang, Tsin-Yuan Chang:
A Built-In Parametric Timing Measurement Unit. IEEE Des. Test Comput. 21(4): 322-330 (2004) - [c13]Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee:
An SOC Test Integration Platform and Its Industrial Realization. ITC 2004: 1213-1222 - 2002
- [c12]Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin:
Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium 2002: 356- - [c11]Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin:
Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium 2002: 411- - [c10]Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang:
Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm. DFT 2002: 117-128 - 2001
- [c9]Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu:
Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. Asian Test Symposium 2001: 91-96 - [c8]Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang:
A low-cost CMOS time interval measurement core. ISCAS (4) 2001: 190-193 - [c7]Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang:
A built-in timing parametric measurement unit. ITC 2001: 315-322 - [c6]Jing-Reng Huang, Madhu K. Iyer, Kwang-Ting Cheng:
A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. VTS 2001: 198-203 - [c5]Wei-Cheng Lai, Jing-Reng Huang, Kwang-Ting (Tim) Cheng:
Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses. VTS 2001: 204-209 - 2000
- [c4]Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu:
A programmable built-in self-test core for embedded memories. ASP-DAC 2000: 11-12 - [c3]Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu:
An FPGA-based re-configurable functional tester for memory chips. Asian Test Symposium 2000: 51-57 - [c2]Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang:
A realistic fault model for flash memories. Asian Test Symposium 2000: 274-281 - [c1]Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai:
BRAINS: A BIST Compiler for Embedded Memories. DFT 2000: 299-
1990 – 1999
- 1999
- [j1]Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang:
A Programmable BIST Core for Embedded DRAM. IEEE Des. Test Comput. 16(1): 59-70 (1999)
Coauthor Index
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