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Hideo Toyoshima
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2000 – 2009
- 2002
- [j7]Junichi Yamada, Tohru Miwa, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiko Maejima, Hiromitsu Hada, Hidemitsu Mori, Seiichi Takahashi, Hidenori Takeuchi, Takemitsu Kunio:
A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers. IEEE J. Solid State Circuits 37(8): 1073-1079 (2002) - 2001
- [j6]Kenji Noda, Koichi Takeda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hideaki Kawamoto, Nobuyuki Ikezawa, Yoshiharu Aimoto, Noritsugu Nakamura, Takahiro Iwasaki, Hideo Toyoshima, Tadahiko Horiuchi:
An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield. IEEE J. Solid State Circuits 36(3): 510-515 (2001) - [j5]Tohru Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiko Maejima, Hiromitsu Hada, Takemitsu Kunio:
NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors. IEEE J. Solid State Circuits 36(3): 522-527 (2001) - [c3]Hideo Toyoshima, Sota Kobayashi, Junichi Yamada, Tohru Miwa, Hiroki Koike, Hidenori Takeuchi, Hidemitsu Mori, Naoki Kasai, Yukihiko Maejima, Nobuhira Tanabe, Toru Tatsumi, Hiromitsu Hada:
FeRAM device and circuit technologies fully compatible with advanced CMOS. CICC 2001: 171-178 - 2000
- [j4]Koichi Takeda, Yoshiharu Aimoto, Noritsugu Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Kenji Noda, Koujirou Matsui, Shinya Itoh, Sadaaki Masuoka, Tadahiko Horiuchi, Atsushi Nakagawa, Kenju Shimogawa, Hiroyuki Takahashi:
A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro. IEEE J. Solid State Circuits 35(11): 1631-1640 (2000) - [c2]Tohm Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Tom Tatsumi, Yukihiro Maejima, Hiromitsu Hada, Takemitsu Kunio:
NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors. CICC 2000: 65-68 - [c1]Kenji Noda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hiroyuki Kawamoto, Nobuyuki Ikezawa, Koichi Takeda, Yoshiharu Aimoto, Naoto Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Tadahiko Horiuchi:
An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield. CICC 2000: 283-286
1990 – 1999
- 1997
- [j3]Kazuyuki Nakamura, Koichi Takeda, Hideo Toyoshima, Kenji Noda, Hiroaki Ohkubo, Tetsuya Uchida, Toshiyuki Shimizu, Toshiro Itani, Ken Tokashiki, Koji Kishimoto:
A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O. IEEE J. Solid State Circuits 32(11): 1758-1765 (1997) - 1996
- [j2]Hideo Toyoshima, Shigeru Kuhara, Koichi Takeda, Kazuyuki Nakamura, Hiloshi Okamura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki:
A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM. IEEE J. Solid State Circuits 31(11): 1610-1617 (1996) - 1995
- [j1]Hitoshi Okamura, Hideo Toyoshima, Koichi Takeda, Takashi Oguri, Satoshi Nakamura, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Hiroshi Yoshida, Tom Yamazaki:
A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors. IEEE J. Solid State Circuits 30(11): 1196-1202 (1995)
Coauthor Index
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