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Shreya Kundu
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2020 – today
- 2024
- [c12]Taras Ravsher, Robin Degraeve, Daniele Garbin, Sergiu Clima, Andrea Fantini, Gabriele Luca Donadio, Shreya Kundu, Wouter Devulder, Hubert Hody, Goedele Potoms, Jan Van Houdt, Valeri Afanas'ev, Attilio Belmonte, Gouri Sankar Kar:
Comprehensive Performance and Reliability Assessment of Se-based Selector-Only Memory. IRPS 2024: 7 - [c11]Anshul Gupta, Shreya Kundu, Stefan Decoster, K. Sah, G. Delie, B. Truijen, Davide Tierno, Giulio Marti, O. Varela Pedreira, B. Kenens, Y. Hermans, C. Adelmann, B. de Wachter, Ivan Ciofi, G. Murdoch, A. Cross, Seongho Park, Zsolt Tokei:
Mitigating Line-Break Defectivity with a Sandwiched TiN or W Layer for Metal Pitch 18 NM Aspect Ratio 6 Semi-Damascene Interconnects. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c10]Attilio Belmonte, Shreya Kundu, S. Subhechha, Adrian Vaisman Chasin, Nouredine Rassoul, Harold Dekkers, H. Puliyalil, F. Seidel, P. Carolan, Romain Delhougne, Gouri Sankar Kar:
Lowest IOFF < 3×10-21 A/μm in capacitorless DRAM achieved by Reactive Ion Etch of IGZO-TFT. VLSI Technology and Circuits 2023: 1-2 - [c9]Souvik Ghosh
, Quentin Smets, S. Banerjee, Tom Schram, K. Kennes, R. Verheyen, P. Kumar, M.-E. Boulon, Benjamin Groven, H. M. Silva, Shreya Kundu, Daire Cott, Dennis Lin, P. Favia, T. Nuytten, A. Phommahaxay, Inge Asselberghs, C. De La Rosa, Gouri Sankar Kar, Steven Brems:
Integration of epitaxial monolayer MX₂ channels on 300mm wafers via Collective-Die-To-Wafer (CoD2W) transfer. VLSI Technology and Circuits 2023: 1-2 - [c8]Shreya Kundu, D. H. van Doip, Tom Schram, Quentin Smets, S. Banerjee, Benjamin Groven, Daire Cott, Stefan Decoster, P. Bezard, F. Lazzarino, K. Banerjee, Souvik Ghosh
Towards low damage and fab-compatible top-contacts in MX2 transistors using a combined synchronous pulse atomic layer etch and wet-chemical etch approach. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c7]S. Subhechha, Nouredine Rassoul, Attilio Belmonte, Hubert Hody, Harold Dekkers, Michiel J. van Setten, Adrian Vaisman Chasin, Shamin H. Sharifi, K. Banerjee, H. Puliyalil, Shreya Kundu, M. Pak, D. Tsvetanova, Nina Bazzazian, Kevin Vandersmissen, D. Batuk, J. Geypen, J. Heijlen, Romain Delhougne, Gouri Sankar Kar:
Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control. ICICDT 2022: 88 - [c6]Gayle Murdoch, Matin O'Toole, Giulio Marti, Ankit Pokhrel, Diana Tsvetanova, Stefan Decoster, Shreya Kundu, Yusuke Oniki, Arame Thiam, Quoc Toan Le
First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP. VLSI Technology and Circuits 2022: 1-2 - [c5]S. Subhechha, Nouredine Rassoul, Attilio Belmonte, Hubert Hody, Harold Dekkers, Michiel J. van Setten, Adrian Vaisman Chasin, Shamin H. Sharifi, S. Sutar, L. Magnarin, Umberto Celano
Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for Vt > 0 V and Ion > 30 µA/µm. VLSI Technology and Circuits 2022: 292-293 - [c4]Taras Ravsher
Enhanced performance and low-power capability of SiGeAsSe-GeSbTe 1S1R phase-change memory operated in bipolar mode. VLSI Technology and Circuits 2022: 312-313 - 2021
- [c3]Sidharth Rao
STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application. IMW 2021: 1-4 - [c2]Simon Van Beek, Siddharth Rao
Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution. IRPS 2021: 1-5
2010 – 2019
- 2018
- [c1]Kevin Garello, Kevin Garello Yasin, S. Couet, Laurent Souriau
SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories. VLSI Circuits 2018: 81-82 - [i1]Kevin Garello, Farrukh Yasin, S. Couet, Laurent Souriau, Johan Swerts, Sidharth Rao, Simon Van Beek, Wonsub Kim, Enlong Liu, Shreya Kundu, Diana Tsvetanova, N. Jossart, Kris Croes, E. Grimaldi, M. Baumgartner, D. Crotti, Arnaud Furnémont, Pietro Gambardella, Gouri Sankar Kar:
SOT-MRAM 300mm integration for low power and ultrafast embedded memories. CoRR abs/1810.10356 (2018)
Coauthor Index
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