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Seungwoo Park
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2020 – today
- 2024
- [j16]Hyunjin Kim
, ChangHun Park, Inho Park
A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications. IEEE J. Solid State Circuits 59(2): 551-562 (2024) - [j15]Jonghyuck Choi
A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces. IEEE J. Solid State Circuits 59(4): 1261-1270 (2024) - [j14]Jincheol Sim
A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10- and 100-m Distances. IEEE J. Solid State Circuits 59(6): 1835-1846 (2024) - [j13]Jincheol Sim
A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques. IEEE J. Solid State Circuits 59(8): 2518-2528 (2024) - [j12]Seongcheol Kim
Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces. IEEE J. Solid State Circuits 59(10): 3432-3443 (2024) - [j11]Seongcheol Kim
A 0.458-pJ/bit 24-Gb/s/pin Capacitively Driven PAM-4 Transceiver With PAM-Based Crosstalk Cancellation for High-Density Die-to-Die Interfaces. IEEE J. Solid State Circuits 59(11): 3730-3740 (2024) - [j10]Hyoshin Kang
A 13-Gb/s Single-Ended NRZ Receiver With 1-Sample Per 2-UI Using Data Edge Sampling for Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3328-3332 (2024) - [j9]Seungwoo Park, Yoonjae Choi
A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling. IEEE Trans. Circuits Syst. II Express Briefs 71(9): 4096-4100 (2024) - 2023
- [j8]Yoonjae Choi
A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces. IEEE J. Solid State Circuits 58(7): 2005-2015 (2023) - [j7]Youngwook Kwon, Hyunsu Park, Yoonjae Choi
A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces. IEEE J. Solid State Circuits 58(8): 2314-2325 (2023) - [j6]Yoonjae Choi
A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2734-2743 (2023) - [j5]Jonghyuck Choi
A 16-Gb/s NRZ Receiver With 0.0019-pJ/bit/dB 1-Tap Charge-Redistribution DFE. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 904-908 (2023) - [c1]Seungwoo Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Hyunsu Park, Youngwook Kwon, Chulwoo Kim:
A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications. ISSCC 2023: 118-119 - 2022
- [j4]Jonghyuck Choi
Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 69(8): 3416-3427 (2022) - [j3]Youngwook Kwon, Hyunsu Park, Yoonjae Choi
A 15 Gb/s Non-Return-to-Zero Transmitter With 1-Tap Pre-Emphasis Feed-Forward Equalizer for Low-Power Ground Terminated Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2737-2741 (2022) - 2021
- [j2]Hyunsu Park, Jincheol Sim, Yoonjae Choi
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. IEEE J. Solid State Circuits 56(6): 1886-1896 (2021)
2010 – 2019
- 2019
- [j1]Tae Hoon Do, Seungwoo Park
M-folding method-based elliptic curve cryptosystem for industrial cyber-physical system. Int. J. Distributed Sens. Networks 15(10) (2019)
Coauthor Index
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