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Sheng Li 0007
Person information
- affiliation: Google, Mountain View, CA, USA
- affiliation (former): Intel Labs, Santa Clara, CA, USA
- affiliation (former): Hewlett-Packard Labs
- affiliation (former): University of Notre Dame, IN, USA
Other persons with the same name
- Sheng Li — disambiguation page
- Sheng Li 0001
— University of Virginia, Charlottesville, VA, USA (and 3 more)
- Sheng Li 0002
- Sheng Li 0003 — Harbin Institute of Technology, Laboratory of Machine Intelligence and Translation, China
- Sheng Li 0005
- Sheng Li 0006
- Sheng Li 0008
- Sheng Li 0009 — Xijing University, Xi'an, China (and 1 more)
- Sheng Li 0010
- Sheng Li 0011
- Sheng Li 0012
- Sheng Li 0013
- Sheng Li 0014 — Karlsruhe Institute of Technology, Germany
- Sheng Li 0015
- Sheng Li 0016
- Sheng Li 0017 — Alibaba Inc., Hangzhou, China (and 1 more)
- Sheng Li 0018
- Sheng Li 0019 — University of Pittsburgh, PA, USA (and 1 more)
- Sheng Li 0020
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2020 – today
- 2024
- [c24]Jordan Dotzel, Yuzong Chen, Bahaa Kotb, Sushma Prasad, Gang Wu, Sheng Li, Mohamed S. Abdelfattah, Zhiru Zhang:
Learning from Students: Applying t-Distributions to Explore Accurate and Efficient Formats for LLMs. ICML 2024 - [c23]Hong Liu, Ryohei Urata, Kevin Yasumura, Xiang Zhou, Roy Bannon, Jill Berger, Pedram Dashti, Norm Jouppi, Cedric F. Lam, Sheng Li, Erji Mao, Daniel Nelson, George Papen, Muhammad Mukarram Bin Tariq, Amin Vahdat:
Reconfigurable Lightwave Fabrics for ML Supercomputers. OFC 2024: 1-3 - [i7]Jordan Dotzel, Yuzong Chen, Bahaa Kotb, Sushma Prasad, Gang Wu, Sheng Li, Mohamed S. Abdelfattah, Zhiru Zhang:
Learning from Students: Applying t-Distributions to Explore Accurate and Efficient Formats for LLMs. CoRR abs/2405.03103 (2024) - 2023
- [c22]Sheng Li, Garrett Andersen, Tao Chen, Liqun Cheng, Julian Grady, Da Huang, Quoc V. Le, Andrew Li, Xin Li, Yang Li, Chen Liang, Yifeng Lu, Yun Ni
Hyperscale Hardware Optimized Neural Architecture Search. ASPLOS (3) 2023: 343-358 - [c21]Cheng Fu, Hanxian Huang, Zixuan Jiang, Yun Ni, Lifeng Nai, Gang Wu, Liqun Cheng, Yanqi Zhou, Sheng Li, Andrew Li, Jishen Zhao:
TripLe: Revisiting Pretrained Model Reuse and Progressive Learning for Efficient Vision Transformer Scaling and Searching. ICCV 2023: 17107-17117 - [c20]Norman P. Jouppi
TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings. ISCA 2023: 82:1-82:14 - [c19]Hong Liu
Lightwave Fabrics: At-Scale Optical Circuit Switching for Datacenter and Machine Learning Systems. SIGCOMM 2023: 499-515 - [i6]Norman P. Jouppi, George Kurian, Sheng Li, Peter C. Ma, Rahul Nagarajan, Lifeng Nai, Nishant Patil, Suvinay Subramanian, Andy Swing, Brian Towles, Cliff Young, Xiang Zhou, Zongwei Zhou, David A. Patterson:
TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings. CoRR abs/2304.01433 (2023) - [i5]Jordan Dotzel, Gang Wu, Andrew Li, Muhammad Umar
FLIQS: One-Shot Mixed-Precision Floating-Point and Integer Quantization Search. CoRR abs/2308.03290 (2023) - [i4]Yongqi Huang, Peng Ye, Xiaoshui Huang, Sheng Li, Tao Chen, Tong He, Wanli Ouyang:
Experts Weights Averaging: A New General Training Scheme for Vision Transformers. CoRR abs/2308.06093 (2023) - 2021
- [j9]Thomas Norrie
The Design Process for Google's Training Chips: TPUv2 and TPUv3. IEEE Micro 41(2): 56-63 (2021) - [c18]Sheng Li, Mingxing Tan, Ruoming Pang, Andrew Li, Liqun Cheng, Quoc V. Le, Norman P. Jouppi:
Searching for Fast Model Families on Datacenter Accelerators. CVPR 2021: 8085-8095 - [c17]Tianqi Tang, Sheng Li, Lifeng Nai, Norman P. Jouppi, Yuan Xie:
NeuroMeter: An Integrated Power, Area, and Timing Modeling Framework for Machine Learning Accelerators Industry Track Paper. HPCA 2021: 841-853 - [c16]Norman P. Jouppi, Doe Hyun Yoon, Matthew Ashcraft, Mark Gottscho, Thomas B. Jablin, George Kurian, James Laudon, Sheng Li, Peter C. Ma, Xiaoyu Ma, Thomas Norrie, Nishant Patil, Sushma Prasad, Cliff Young, Zongwei Zhou, David A. Patterson:
Ten Lessons From Three Generations Shaped Google's TPUv4i : Industrial Product. ISCA 2021: 1-14 - [i3]Sheng Li, Mingxing Tan, Ruoming Pang, Andrew Li, Liqun Cheng, Quoc V. Le, Norman P. Jouppi:
Searching for Fast Model Families on Datacenter Accelerators. CoRR abs/2102.05610 (2021) - 2020
- [j8]Norman P. Jouppi, Doe Hyun Yoon, George Kurian, Sheng Li, Nishant Patil, James Laudon, Cliff Young, David A. Patterson:
A domain-specific supercomputer for training deep neural networks. Commun. ACM 63(7): 67-78 (2020) - [c15]Thomas Norrie, Nishant Patil, Doe Hyun Yoon, George Kurian, Sheng Li, James Laudon, Cliff Young, Norman P. Jouppi, David A. Patterson:
Google's Training Chips Revealed: TPUv2 and TPUv3. Hot Chips Symposium 2020: 1-70
2010 – 2019
- 2019
- [j7]Shihao Ji
Parallelizing Word2Vec in Shared and Distributed Memory. IEEE Trans. Parallel Distributed Syst. 30(9): 2090-2100 (2019) - 2017
- [c14]Eojin Lee, Jongwook Chung, Daejin Jung, Sukhan Lee, Sheng Li, Jung Ho Ahn
Work as a team or individual: Characterizing the system-level impacts of main memory partitioning. IISWC 2017: 156-166 - 2016
- [j6]Daejin Jung, Sheng Li, Jung Ho Ahn
Large Pages on Steroids: Small Ideas to Accelerate Big Memory Applications. IEEE Comput. Archit. Lett. 15(2): 101-104 (2016) - [j5]Sheng Li, Hyeontaek Lim, Victor W. Lee, Jung Ho Ahn
Achieving One Billion Key-Value Requests per Second on a Single Server. IEEE Micro 36(3): 94-104 (2016) - [j4]Sheng Li, Hyeontaek Lim, Victor W. Lee, Jung Ho Ahn
Full-Stack Architecting to Achieve a Billion-Requests-Per-Second Throughput on a Single Key-Value Store Server Platform. ACM Trans. Comput. Syst. 34(2): 5:1-5:30 (2016) - [i2]Shihao Ji, Nadathur Satish, Sheng Li, Pradeep Dubey:
Parallelizing Word2Vec in Shared and Distributed Memory. CoRR abs/1604.04661 (2016) - [i1]Shihao Ji, Nadathur Satish, Sheng Li, Pradeep Dubey:
Parallelizing Word2Vec in Multi-Core and Many-Core Architectures. CoRR abs/1611.06172 (2016) - 2015
- [j3]Jishen Zhao, Sheng Li, Jichuan Chang, John L. Byrne, Laura L. Ramirez, Kevin T. Lim, Yuan Xie, Paolo Faraboschi:
Buri: Scaling Big-Memory Computing with Hardware-Based Memory Expansion. ACM Trans. Archit. Code Optim. 12(3): 31:1-31:24 (2015) - [c13]Ke Chen, Sheng Li, Jung Ho Ahn
History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures. ICS 2015: 251-261 - [c12]Sheng Li, Hyeontaek Lim, Victor W. Lee, Jung Ho Ahn
Architecting to achieve a billion requests per second throughput on a single key-value store server platform. ISCA 2015: 476-488 - 2013
- [j2]Sheng Li, Jung Ho Ahn
The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing. ACM Trans. Archit. Code Optim. 10(1): 5:1-5:29 (2013) - [c11]Jung Ho Ahn
McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling. ISPASS 2013: 74-85 - [c10]Jishen Zhao, Sheng Li, Doe Hyun Yoon, Yuan Xie, Norman P. Jouppi:
Kiln: closing the performance gap between systems with and without persistence support. MICRO 2013: 421-432 - 2012
- [c9]Ke Chen, Sheng Li, Naveen Muralimanohar, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi:
CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory. DATE 2012: 33-38 - [c8]Sheng Li, Doe Hyun Yoon, Ke Chen, Jishen Zhao, Jung Ho Ahn
MAGE: adaptive granularity and ECC for resilient and power efficient memory systems. SC 2012: 33 - 2011
- [j1]Sheng Li, Shannon K. Kuntz, Jay B. Brockman, Peter M. Kogge:
Lightweight Chip Multi-Threading (LCMT): Maximizing Fine-Grained Parallelism On-Chip. IEEE Trans. Parallel Distributed Syst. 22(7): 1178-1191 (2011) - [c7]Sheng Li, Ke Chen, Jung Ho Ahn
CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques. ICCAD 2011: 694-701 - [c6]Sheng Li, Kevin T. Lim, Paolo Faraboschi
System-level integrated server architectures for scale-out datacenters. MICRO 2011: 260-271 - [c5]Sheng Li, Ke Chen, Ming-yu Hsieh, Naveen Muralimanohar, Chad D. Kersey, Jay B. Brockman, Arun F. Rodrigues, Norman P. Jouppi:
System implications of memory reliability in exascale computing. SC 2011: 46:1-46:12
2000 – 2009
- 2009
- [c4]Sheng Li, Jung Ho Ahn
McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. MICRO 2009: 469-480 - 2008
- [c3]Jay B. Brockman, Sheng Li, Peter M. Kogge, Amit Kashyap, Mohammad M. Mojarradi:
Design of a mask-programmable memory/multiplier array using G4-FET technology. DAC 2008: 337-338 - [c2]Sheng Li, Shannon K. Kuntz, Peter M. Kogge, Jay B. Brockman:
Memory model effects on application performance for a lightweight multithreaded architecture. IPDPS 2008: 1-8 - 2007
- [c1]Sheng Li, Amit Kashyap, Shannon K. Kuntz, Jay B. Brockman, Peter M. Kogge, Paul L. Springer, Gary Block:
A Heterogeneous Lightweight Multithreaded Architecture. IPDPS 2007: 1-8
Coauthor Index
aka: Norm Jouppi
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