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Serge Vernalde
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2000 – 2009
- 2004
- [j6]Théodore Marescaux, Vincent Nollet, Jean-Yves Mignolet, T. Andrei Bartic, W. Moffat, Prabhat Avasare, Paul Coene, Diederik Verkest, Serge Vernalde, Rudy Lauwereins:
Run-time support for heterogeneous multitasking on reconfigurable SoCs. Integr. 38(1): 107-130 (2004) - [j5]Javier Resano
, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor:
A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs. Microprocess. Microsystems 28(5-6): 291-301 (2004) - [c40]Vincent Nollet, Théodore Marescaux, Diederik Verkest, Jean-Yves Mignolet, Serge Vernalde:
Operating-system controlled network on chip. DAC 2004: 256-259 - [c39]Bingfeng Mei, Serge Vernalde, Diederik Verkest, Rudy Lauwereins:
Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study. DATE 2004: 1224-1229 - [c38]T. Andrei Bartic, Dirk Desmet, Jean-Yves Mignolet, Théodore Marescaux, Diederik Verkest, Serge Vernalde, Rudy Lauwereins, J. Miller, Frédéric Robert:
Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation. FPL 2004: 637-647 - [c37]Steven J. E. Wilton, Noha Kafafi, Bingfeng Mei, Serge Vernalde:
Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays. FPT 2004: 33-40 - [e1]Jürgen Becker, Marco Platzner, Serge Vernalde:
Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings. Lecture Notes in Computer Science 3203, Springer 2004, ISBN 3-540-22989-2 [contents] - 2003
- [c36]Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins:
Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling. DATE 2003: 10296-10301 - [c35]Jean-Yves Mignolet, Vincent Nollet, Paul Coene, Diederik Verkest, Serge Vernalde, Rudy Lauwereins:
Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip. DATE 2003: 10986-10993 - [c34]Vincent Nollet, Jean-Yves Mignolet, T. Andrei Bartic, Diederik Verkest, Serge Vernalde, Rudy Lauwereins:
Hierarchical Run-Time Reconfiguration Managed by an Operating System for Reconfigurable Systems. Engineering of Reconfigurable Systems and Algorithms 2003: 81-87 - [c33]Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor:
Run-Time Scheduling for Multimedia Applications on Dynamically Reconfigurable Systems. ESTIMedia 2003: 156-162 - [c32]Javier Resano
Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms. FCCM 2003: 278-279 - [c31]Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins:
ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. FPL 2003: 61-70 - [c30]Javier Resano, Daniel Mozos, Diederik Verkest, Serge Vernalde, Francky Catthoor:
Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems. FPL 2003: 585-594 - [c29]Théodore Marescaux, Jean-Yves Mignolet, T. Andrei Bartic, W. Moffat, Diederik Verkest, Serge Vernalde, Rudy Lauwereins:
Networks on Chip as Hardware Components of an OS for Reconfigurable Systems. FPL 2003: 595-605 - [c28]Vivek Nema, Bart van Poucke, Miguel Glassee, Serge Vernalde:
Flexible system model and architectural exploration for HIPERLAN 2 DLC wireless LAN protocol. ICC 2003: 111-115 - [c27]Nam Pham Ngoc, Gauthier Lafruit, Jean-Yves Mignolet, Serge Vernalde, Geert Deconinck
A framework for mapping scalable networked applications on run-time reconfigurable platforms. ICME 2003: 469-472 - [c26]Vincent Nollet, Paul Coene, Diederik Verkest, Serge Vernalde, Rudy Lauwereins:
Designing an Operating System for a Heterogeneous Reconfigurable So. IPDPS 2003: 174 - [c25]T. Andrei Bartic, Jean-Yves Mignolet, Vincent Nollet, Théodore Marescaux, Diederik Verkest, Serge Vernalde, Rudy Lauwereins:
Highly scalable network on chip for reconfigurable systems. SoC 2003: 79-82 - [c24]Richard Stahl, Robert Pasko, Luc Rijnders, Diederik Verkest, Serge Vernalde, Rudy Lauwereins, Francky Catthoor:
Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java. SCOPES 2003: 313-328 - 2002
- [j4]Yajun Ha, Serge Vernalde, Patrick Schaumont
Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. J. Supercomput. 21(2): 131-144 (2002) - [c23]Robert Pasko, Serge Vernalde, Patrick Schaumont
Techniques to Evolve a C++ Based System Design Language. DATE 2002: 302-309 - [c22]Théodore Marescaux, T. Andrei Bartic, Diederik Verkest, Serge Vernalde, Rudy Lauwereins:
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs. FPL 2002: 795-805 - [c21]Yajun Ha, Radovan Hipik, Serge Vernalde, Diederik Verkest, Marc Engels
Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications. FPL 2002: 1135-1138 - [c20]Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins:
DRESC: a retargetable compiler for coarse-grained reconfigurable architectures. FPT 2002: 166-173 - 2001
- [j3]Robert Pasko, Luc Rijnders, Patrick R. Schaumont, Serge A. Vernalde, Daniela Duracková:
High-performance flexible all-digital quadrature up and down converter chip. IEEE J. Solid State Circuits 36(3): 408-416 (2001) - [c19]Yajun Ha, Geert Vanmeerbeeck, Patrick Schaumont
Virtual Java/FPGA interface for networked reconfiguration. ASP-DAC 2001: 558-563 - [c18]Radim Cmar, Robert Pasko, Jean-Yves Mignolet, Geert Vanmeerbeeck, Patrick Schaumont, Serge Vernalde:
Platform design approach for re-configurable network appliances. CICC 2001: 79-82 - [c17]Geert Vanmeerbeeck, Patrick Schaumont
Hardware/software partitioning of embedded system in OCAPI-xl. CODES 2001: 30-35 - [c16]Yajun Ha, Patrick Schaumont
A SW/HW Interface API for Java/FPGA Co-Designed Applets. FCCM 2001: 269-270 - [c15]Yajun Ha, Bingfeng Mei, Patrick Schaumont, Serge Vernalde, Rudy Lauwereins, Hugo De Man:
Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware. FPL 2001: 264-274 - 2000
- [c14]Robert Pasko, Luc Rijnders, Patrick Schaumont, Serge Vernalde, Daniela Duracková:
High-performance flexible all-digital quadrature up and down converter chip. CICC 2000: 43-46 - [c13]Robert Pasko, Radim Cmar, Patrick Schaumont
Functional verification of an embedded network component by co-simulation with a real network. HLDVT 2000: 64-67 - [c12]Yajun Ha, Serge Vernalde, Patrick Schaumont, Marc Engels, Hugo De Man:
Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. PDPTA 2000 - [c11]Yajun Ha, Patrick Schaumont
A Hardware Virtual Machine for the Networked Reconfiguration. IEEE International Workshop on Rapid System Prototyping 2000: 194-199
1990 – 1999
- 1999
- [j2]Robert Pasko, Patrick Schaumont
A new algorithm for elimination of common subexpressions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(1): 58-68 (1999) - [c10]Patrick Schaumont
A 10 Mbit/s Upstream Cable Modem with Automatic equalization. DAC 1999: 337-340 - [c9]Patrick Schaumont
Hardware Reuse at the Behavioral Level. DAC 1999: 784-789 - [c8]Radim Cmar, Luc Rijnders, Patrick Schaumont
A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement. DATE 1999: 271- - 1998
- [j1]Patrick Schaumont
Low Power Digital Frequency Conversion Architectures. J. VLSI Signal Process. 18(2): 187-197 (1998) - [c7]Patrick Schaumont
A Programming Environment for the Design of Complex High Speed ASICs. DAC 1998: 315-320 - [c6]Patrick Schaumont
A Technique for Combined Virtual Prototyping and Hardware Design. International Workshop on Rapid System Prototyping 1998: 156-161 - 1997
- [c5]Radim Cmar, Serge Vernalde:
Highly scalable parallel parametrizable architecture of the motion estimator. ED&TC 1997: 208-212 - [c4]Patrick Schaumont
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications. ED&TC 1997: 542-546 - 1996
- [c3]Elisabeth Berrebi, Polen Kission, Serge Vernalde, S. De Troch, Jean-Claude Herluison, Jean Fréhel, Ahmed Amine Jerraya, Ivo Bolsens:
Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis. DAC 1996: 573-578 - [c2]Jan Bormans, Serge Vernalde, Jan Cornelis, Ivo Bolsens, Hugo De Man:
A Hilbert fractal codec for region oriented compression of color images. ICECS 1996: 41-44 - 1994
- [c1]Koen Van Nieuwenhove, Kjell Cools, D. Devisch, Ivo Bolsens, Serge Vernalde, Kim Chansik, R. B. W. Lee, Oh Younguk:
ASIC synthesis of a flexible 80 Mbit/s Reed-Solomon Codec. EURO-DAC 1994: 658-663
Coauthor Index
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