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Masanori Hayashikoshi
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2020 – today
- 2020
- [j7]Takashi Nakada, Hiroyuki Yanagihashi
, Kunimaro Imai, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi, Hiroshi Nakamura
An Energy-Efficient Task Scheduling for Near Real-Time Systems on Heterogeneous Multicore Processors. IEICE Trans. Inf. Syst. 103-D(2): 329-338 (2020)
2010 – 2019
- 2019
- [j6]Masanori Hayashikoshi, Hiroaki Tanizaki, Yasumitsu Murai, Takaharu Tsuji, Kiyoshi Kawabata, Koji Nii, Hideyuki Noda, Hiroyuki Kondo, Yoshio Matsuda, Hideto Hidaka:
A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications. IEICE Trans. Electron. 102-C(4): 287-295 (2019) - 2018
- [j5]Masanori Hayashikoshi
Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications. IEEE Trans. Multi Scale Comput. Syst. 4(4): 784-792 (2018) - [c9]Junichi Suzuki, Junichi Yamashita, Masami Hanyu, Masamichi Ido, Tatsuya Saito, Yasuhiro Nakashima, Masanori Hayashikoshi, Yukiyoshi Kiyota:
A Cost-Effective High Accuracy Auto-Trimming System without Tester Constraint for Low-End Embedded Flash Memory. ISOCC 2018: 48-49 - 2017
- [j4]Takashi Nakada, Tomoki Hatanaka, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura
An Energy-Efficient Task Scheduling for Near-Realtime Systems with Execution Time Variation. IEICE Trans. Inf. Syst. 100-D(10): 2493-2504 (2017) - [c8]Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Koji Nii, Hiroyuki Kondo:
Low-power multi-sensor system with task scheduling and autonomous standby mode transition control for IoT applications. COOL Chips 2017: 1-3 - [c7]Takashi Nakada, Hiroyuki Yanagihashi
Energy-aware task scheduling for near real-time periodic tasks on heterogeneous multicore processors. VLSI-SoC 2017: 1-6 - 2016
- [c6]Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Hiroyuki Kondo:
Low-power multi-sensor system with normally-off sensing technology for IoT applications. ISOCC 2016: 195-196 - [c5]Takashi Nakada, Tomoki Hatanaka, Hiroshi Nakamura
An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis. VLSI-SoC 2016: 1-7 - 2015
- [c4]Takashi Nakada, Hiroyuki Yanagihashi
Energy-Efficient Continuous Task Scheduling for Near Real-Time Periodic Tasks. DSDIS 2015: 675-681 - 2014
- [j3]Takashi Nakada, Kazuya Okamoto, Toshiya Komoda, Shinobu Miwa, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura:
Design Aid of Multi-core Embedded Systems with Energy Model. Inf. Media Technol. 9(4): 419-428 (2014) - [c3]Masanori Hayashikoshi, Yohei Sato, Hiroshi Ueki, Hiroyuki Kawai, Toru Shimizu:
Normally-off MCU architecture for low-power sensor node. ASP-DAC 2014: 12-16 - [c2]Takashi Nakada, Takuya Shigematsu, Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura
Data-aware power management for periodic real-time systems with non-volatile memory. NVMSA 2014: 1-6
1990 – 1999
- 1993
- [j2]Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima:
Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. IEEE Des. Test Comput. 10(2): 6-12 (1993) - 1992
- [c1]Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima:
A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. ITC 1992: 615-622
1980 – 1989
- 1989
- [j1]Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Masanori Hayashikoshi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara:
120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs. IEEE J. Solid State Circuits 24(5): 1244-1249 (1989)
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