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Salim Ullah
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2020 – today
- 2024
- [j13]Salim Ullah
, Siva Satyendra Sahoo
AxOSpike: Spiking Neural Networks-Driven Approximate Operator Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(11): 3324-3335 (2024) - [j12]Siva Satyendra Sahoo
AxOCS: Scaling FPGA-Based Approximate Operators Using Configuration Supersampling. IEEE Trans. Circuits Syst. I Regul. Pap. 71(6): 2646-2659 (2024) - [j11]Siva Satyendra Sahoo
AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming. ACM Trans. Reconfigurable Technol. Syst. 17(2): 31:1-31:28 (2024) - [c21]Salim Ullah, Siva Satyendra Sahoo, Akash Kumar:
Enabling Energy-efficient AI Computing: Leveraging Application-specific Approximations : (Education Class). CASES 2024: 3-4 - [c20]Siddharth Gupta, Salim Ullah, Akash Kumar:
LeQC-At: Learning Quantization Configurations During Adversarial Training for Robust Deep Neural Networks. DSD 2024: 495-502 - [c19]Yuhao Liu
BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators. FCCM 2024: 220 - 2023
- [j10]Yuankang Zhao
NvMISC: Toward an FPGA-Based Emulation Platform for RISC-V and Nonvolatile Memories. IEEE Embed. Syst. Lett. 15(4): 170-173 (2023) - [j9]Yuhao Liu
High-Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers. IEEE Embed. Syst. Lett. 15(4): 194-197 (2023) - [j8]Siva Satyendra Sahoo
AxOTreeS: A Tree Search Approach to Synthesizing FPGA-based Approximate Operators. ACM Trans. Embed. Comput. Syst. 22(5s): 101:1-101:26 (2023) - [c18]Rohit Ranjan, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar:
SyFAxO-GeN: Synthesizing FPGA-Based Approximate Operators with Generative Networks. ASP-DAC 2023: 402-409 - [c17]Salim Ullah
CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators. ACM Great Lakes Symposium on VLSI 2023: 671-677 - [c16]Yuhao Liu
NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs. IPDPS Workshops 2023: 85-92 - [i4]Siva Satyendra Sahoo, Salim Ullah
AxOCS: Scaling FPGA-based Approximate Operators using Configuration Supersampling. CoRR abs/2309.12830 (2023) - [i3]Siva Satyendra Sahoo, Salim Ullah, Akash Kumar:
AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming. CoRR abs/2309.13445 (2023) - 2022
- [b1]Salim Ullah:
Design, Analysis, and Applications of Approximate Arithmetic Modules. Dresden University of Technology, Germany, 2022 - [j7]Salim Ullah
High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(2): 211-224 (2022) - [j6]Salim Ullah
AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems. ACM Trans. Embed. Comput. Syst. 21(3): 29:1-29:31 (2022) - [c15]Negar Neda, Salim Ullah
Multi-Precision Deep Neural Network Acceleration on FPGAs. ASP-DAC 2022: 454-459 - [c14]Amritha Immaneni, Salim Ullah
PosAx-O: Exploring Operator-level Approximations for Posit Arithmetic in Embedded AI/ML. DSD 2022: 214-223 - [c13]Fanny Spagnolo, Salim Ullah, Pasquale Corsonello, Akash Kumar:
ERMES: Efficient Racetrack Memory Emulation System based on FPGA. FPL 2022: 342-349 - [c12]Yuhao Liu
NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture. FPT 2022: 1 - 2021
- [j5]Suresh Nambi
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems. IEEE Access 9: 103691-103708 (2021) - [j4]Salim Ullah
Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators. IEEE Embed. Syst. Lett. 13(2): 41-44 (2021) - [j3]Salim Ullah
Area-Optimized Accurate and Approximate Softcore Signed Multiplier Architectures. IEEE Trans. Computers 70(3): 384-392 (2021) - [j2]Akhil Raj Baranwal
ReLAccS: A Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(9): 1754-1767 (2021) - [c11]Salim Ullah, Siva Satyendra Sahoo
CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems. DAC 2021: 475-480 - [c10]Siva Satyendra Sahoo, Akhil Raj Baranwal
MemOReL: A Memory-oriented Optimization Approach to Reinforcement Learning on FPGA-based Embedded Systems. ACM Great Lakes Symposium on VLSI 2021: 339-346 - 2020
- [j1]Siddharth Gupta
ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks. IEEE Access 8: 118899-118911 (2020) - [c9]Zahra Ebrahimi
LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy. ASP-DAC 2020: 605-610 - [c8]Salim Ullah, Siddharth Gupta, Kapil Ahuja
L2L: A Highly Accurate Log_2_Lead Quantization of Pre-trained Neural Networks. DATE 2020: 979-982 - [c7]Zahra Ebrahimi
SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy. ACM Great Lakes Symposium on VLSI 2020: 151-156 - [c6]Arlene John
An Approximate Binary Classifier for Data Integrity Assessment in IoT Sensors. ICECS 2020: 1-4 - [i2]Suresh Nambi, Salim Ullah, Aditya Lohana, Siva Satyendra Sahoo
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems. CoRR abs/2010.12869 (2020) - [i1]Zahra Ebrahimi, Salim Ullah, Akash Kumar:
SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy. CoRR abs/2011.01148 (2020)
2010 – 2019
- 2019
- [c5]Rahim Ullah, Nadeem Javaid
A Comparative Analysis of Neural Networks and Enhancement of ELM for Short Term Load Forecasting. CISIS 2019: 73-86 - [c4]Adarsha Balaji, Salim Ullah, Anup Das
Design Methodology for Embedded Approximate Artificial Neural Networks. ACM Great Lakes Symposium on VLSI 2019: 489-494 - 2018
- [c3]Salim Ullah, Sanjeev Sripadraj Murthy, Akash Kumar:
SMApproxlib: library of FPGA-based approximate multipliers. DAC 2018: 157:1-157:6 - [c2]Salim Ullah
Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators. DAC 2018: 159:1-159:6 - [c1]Bharath Srinivas Prabakaran, Semeen Rehman, Muhammad Abdullah Hanif, Salim Ullah
DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems. DATE 2018: 917-920
Coauthor Index
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last updated on 2024-12-02 22:29 CET by the dblp team
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