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Tiago D. Perez
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2020 – today
- 2024
- [j4]Zain Ul Abideen
, Rui Wang, Tiago Diadami Perez
Impact of Orientation on the Bias of SRAM-Based PUFs. IEEE Des. Test 41(3): 14-20 (2024) - 2023
- [j3]Tiago D. Perez
Hardware Trojan Insertion in Finalized Layouts: From Methodology to a Silicon Demonstration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2094-2107 (2023) - [j2]Zain Ul Abideen
A Security-Aware and LUT-Based CAD Flow for the Physical Synthesis of hASICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(10): 3157-3170 (2023) - [i9]Mohammad Eslami, Tiago D. Perez, Samuel Pagliarini:
SALSy: Security-Aware Layout Synthesis. CoRR abs/2308.06201 (2023) - [i8]Zain Ul Abideen, Rui Wang, Tiago Diadami Perez, Geert Jan Schrijen, Samuel Pagliarini:
Impact of Orientation on the Bias of SRAM-Based PUFs. CoRR abs/2308.06730 (2023) - 2022
- [c7]Tiago D. Perez, Samuel Pagliarini:
A Side-Channel Hardware Trojan in 65nm CMOS with 2μW precision and Multi-bit Leakage Capability. ASP-DAC 2022: 9-10 - [c6]Tiago D. Perez, Marcio M. Gonçalves, Leonardo Gobatto, Marcelo Brandalero, José Rodrigo Azambuja, Samuel Pagliarini:
G-GPU: A Fully-Automated Generator of GPU-like ASIC Accelerators. DATE 2022: 544-547 - [c5]Alexander Hepp, Tiago D. Perez, Samuel Pagliarini
A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts. ICCAD 2022: 69:1-69:9 - [i7]Zain Ul Abideen, Tiago Diadami Perez, Mayler G. A. Martins, Samuel Pagliarini:
A Security-aware and LUT-based CAD Flow for the Physical Synthesis of eASICs. CoRR abs/2207.05413 (2022) - [i6]Alexander Hepp, Tiago D. Perez, Samuel Pagliarini, Georg Sigl:
A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts. CoRR abs/2208.09235 (2022) - 2021
- [c4]Zain Ul Abideen
From FPGAs to Obfuscated eASICs: Design and Security Trade-offs. AsianHOST 2021: 1-4 - [c3]Tiago D. Perez, Malik Imran
Side-Channel Trojan Insertion - a Practical Foundry-Side Attack via ECO. ISCAS 2021: 1-5 - [i5]Tiago D. Perez, Malik Imran, Pablo Vaz, Samuel Pagliarini:
Side-Channel Trojan Insertion - a Practical Foundry-Side Attack via ECO. CoRR abs/2102.00724 (2021) - [i4]Zain Ul Abideen, Tiago Diadami Perez, Samuel Pagliarini:
From FPGAs to Obfuscated eASICs: Design and Security Trade-offs. CoRR abs/2110.05335 (2021) - [i3]Tiago Diadami Perez, Marcio M. Gonçalves, José Rodrigo Azambuja, Leonardo Gobatto, Marcelo Brandalero, Samuel Pagliarini:
G-GPU: A Fully-Automated Generator of GPU-like ASIC Accelerators. CoRR abs/2111.06166 (2021) - [i2]Tiago D. Perez, Samuel Pagliarini:
Hardware Trojan Insertion in Finalized Layouts: a Silicon Demonstration. CoRR abs/2112.02972 (2021) - 2020
- [j1]Tiago D. Perez
A Survey on Split Manufacturing: Attacks, Defenses, and Challenges. IEEE Access 8: 184013-184035 (2020) - [i1]Tiago D. Perez, Samuel Pagliarini:
A Survey on Split Manufacturing: Attacks, Defenses, and Challenges. CoRR abs/2006.04627 (2020)
2010 – 2019
- 2016
- [c2]Denise C. Alves, Gabriel S. da Silva, Eduardo R. de Lima, Cesar G. Chaves
Architecture design and implementation of key components of an OFDM transceiver for IEEE 802.15.4g. ISCAS 2016: 550-553 - 2015
- [c1]Augusto F. R. Queiroz, Gabriel S. da Silva, Cesar G. Chaves
Demo: FPGA implementation of an IEEE802.15.4g MR-OFDM baseband modem for smart metering utility networks. GCCE 2015: 125-126
Coauthor Index
aka: Samuel Pagliarini
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