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Bijoy Antony Jose
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2020 – today
- 2024
- [j12]Ajai John Chemmanam, Bijoy Antony Jose, Asif Moopan:
Improved multi object tracking with locality sensitive hashing. Pattern Anal. Appl. 27(4): 136 (2024) - [c19]Ajai John Chemmanam, Bijoy Antony Jose, Asif Moopan:
Multi-Modal Learning with Joint Image-Text Embeddings and Decoder Networks. ICPS 2024: 1-6 - 2023
- [j11]Gisha C. G., Ananda Sankar Chakraborty, Rajat Subhra Chakraborty, Bijoy Antony Jose, Jimson Mathew:
A Novel Physical Unclonable Function Based on Hybrid Current Mirror. J. Hardw. Syst. Secur. 7(4): 125-137 (2023) - [j10]Ajai John Chemmanam, Bijoy Antony Jose, Asif Moopan:
A Multi-Tasking Model for Object Detection, Instance Segmentation and Keypoint Estimation Tasks. J. Inf. Sci. Eng. 39(3): 549-560 (2023) - [c18]Gisha C. G., Ananda Sankar Chakraborty, Rajat Subhra Chakraborty, Bijoy Antony Jose, Jimson Mathew:
Diode-Triode Current Mirror Inverter PUF: A Novel Mixed-Signal Low Power Analog PUF. MWSCAS 2023: 1132-1136 - 2022
- [j9]Deepa Mathew, Bijoy Antony Jose:
Real-Time Performance Analysis and Tuning of Embedded System Virtualization Architecture Based on KVM. Int. J. Embed. Real Time Commun. Syst. 13(1): 1-20 (2022) - [c17]Gisha C. G., Bijoy Antony Jose, Jimson Mathew:
A novel mixed-signal PUF based on Current Mirror Inverter. iSES 2022: 89-94 - 2020
- [j8]Deepa Mathew
, Bijoy Antony Jose
Enabling Hardware Performance Counters for Microkernel-Based Virtualization on Embedded Systems. IEEE Access 8: 110550-110564 (2020) - [j7]Nithin P. B., Albert Francis, Ajai John Chemmanam, Bijoy Antony Jose, Jimson Mathew:
Interactive Robotic Testbed for Performance Assessment of Machine Learning based Computer Vision Techniques. J. Inf. Sci. Eng. 36(5): 1055-1067 (2020) - [c16]Ruksin Kamal, Ajai John Chemmanam
Construction Safety Surveillance Using Machine Learning. ISNCC 2020: 1-6 - [c15]Ajish Zacharias, Gisha C. G.
Chaotic Ring Oscillator Based True Random Number Generator Implementations in FPGA. VDAT 2020: 1-6
2010 – 2019
- 2019
- [j6]Rakesh Kumar Sanodiya
A Kernelized Unified Framework for Domain Adaptation. IEEE Access 7: 181381-181395 (2019) - [j5]Jimson Mathew, Bijoy Antony Jose, Priyadarsan Patra
Selected Articles from the ISED 2018 Conference. J. Low Power Electron. 15(2): 160-161 (2019) - [j4]Deepa Mathew, Bijoy Antony Jose, Priyadarsan Patra
Performance Analysis of Microkernel Based Virtualization Techniques on Embedded Systems. J. Low Power Electron. 15(2): 273-281 (2019) - [c14]Grieshma Unnikrishnan, Deepa Mathew, Bijoy Antony Jose, Raju Arvind:
Hybrid Route Recommender System for Smarter Logistics. BigDataSecurity/HPSC/IDS 2019: 239-244 - 2018
- [j3]Jos A. V. Prakash
A Differential Quantizer-Based Error Feedback Modulator for Analog-to-Digital Converters. IEEE Trans. Circuits Syst. II Express Briefs 65-II(1): 21-25 (2018) - [e1]Bijoy Antony Jose, Jimson Mathew:
8th International Symposium on Embedded Computing and System Design, ISED 2018, Cochin, India, December 13-15, 2018. IEEE 2018, ISBN 978-1-5386-6575-6 [contents] - 2017
- [c13]Arya Sahadevan, Deepa Mathew, Jairam Mookathana, Bijoy Antony Jose:
An Offline Online Strategy for IoT Using MQTT. CSCloud 2017: 369-373 - [c12]Deepa Mathew, Bijoy Antony Jose:
Performance analysis of virtualized embedded computing systems. ISED 2017: 1-5 - 2016
- [c11]P. Akhil, C. R. Abhijith, Bijoy Antony Jose:
Interfacing a computer aided design tool with a multi-function numerical machine. ISED 2016: 223-227 - 2015
- [j2]Bijoy Antony Jose, Abhishek Agrawal:
Improving Energy Efficiency of Virtual Machines with Timer Tick Variations. J. Low Power Electron. 11(3): 401-405 (2015) - 2011
- [b1]Bijoy Antony Jose:
Formal Model Driven Software Synthesis for Embedded Systems. Virginia Tech, Blacksburg, VA, USA, 2011 - [c10]Bijoy Antony Jose, Abdoulaye Gamatié, Julien Ouy, Sandeep K. Shukla
SMT based false causal loop detection during code synthesis from Polychronous specifications. MEMOCODE 2011: 109-118 - 2010
- [c9]Bijoy Antony Jose, Jason Pribble, Sandeep K. Shukla
Faster Software Synthesis Using Actor Elimination Techniques for Polychronous Formalism. ACSD 2010: 147-156 - [c8]Bijoy Antony Jose, Sandeep K. Shukla
An alternative polychronous model and synthesis methodology for model-driven embedded software. ASP-DAC 2010: 13-18 - [c7]Mahesh Nanjundappa, Hiren D. Patel, Bijoy Antony Jose, Sandeep K. Shukla:
SCGPSim: a fast SystemC simulator on GPUs. ASP-DAC 2010: 149-154 - [p1]Bijoy Antony Jose, Sandeep K. Shukla
MRICDF: A Polychronous Model for Embedded Software Synthesis. Synthesis of Embedded Software 2010: 173-199
2000 – 2009
- 2009
- [j1]Bijoy Antony Jose, Damu Radhakrishnan:
Redundant binary partial product generators for compact accumulation in Booth multipliers. Microelectron. J. 40(11): 1606-1612 (2009) - [c6]Bijoy Antony Jose, Jason Pribble, Lemaire Stewart, Sandeep K. Shukla:
EmCodeSyn: A visual framework for multi-rate data flow specifications and code synthesis for embedded applications. FDL 2009: 1-6 - [c5]Bijoy Antony Jose, Bin Xue, Sandeep K. Shukla
An Analysis of the Composition of Synchronous Systems. FMGALS@DATE 2009: 69-84 - 2008
- [c4]Syed Suhaib, Bijoy Antony Jose, Sandeep K. Shukla
Formal Transformation of a KPN Specification to a GALS Implementation. FDL 2008: 84-89 - [c3]Bijoy Antony Jose, Sandeep K. Shukla
On the Deterministic Multi-threaded Software Synthesis from Polychronous Specifications. MEMOCODE 2008: 129-138 - [c2]Bijoy Antony Jose, Hiren D. Patel, Sandeep K. Shukla
Generating Multi-Threaded code from Polychronous Specifications. SLAP@ETAPS 2008: 57-69 - 2006
- [c1]Bijoy Antony Jose, Damu Radhakrishnan:
Delay Optimized Redundant Binary Adders. ICECS 2006: 514-517
Coauthor Index
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last updated on 2024-12-01 01:14 CET by the dblp team
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