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Chao-Lin Lee
Person information
- affiliation: National Tsing Hua University, Hsinchu City, Taiwan
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2020 – today
- 2024
- [c12]Chia-Chen Hsu
, Chun-Lin Huang
The Rewriting of DataRaceBench Benchmark for OpenCL Program Validations. ICPP Workshops 2024: 15-22 - [c11]Yi-Fan Chen, Yu-Jen Chang, Ching-Te Chiu, Ming-Long Huang, Geng-Ming Liang, Chao-Lin Lee, Jenq-Kuen Lee, Ping-Yu Hsieh, Wei-Chih Lai:
Low DRAM Memory Access and Flexible Dataflow Convolutional Neural Network Accelerator based on RISC-V Custom Instruction. ISCAS 2024: 1-5 - 2023
- [j5]Chao-Lin Lee
Accelerating AI performance with the incorporation of TVM and MediaTek NeuroPilot. Connect. Sci. 35(1) (2023) - [j4]Chao-Lin Lee
Accelerating AI Applications with Sparse Matrix Compression in Halide. J. Signal Process. Syst. 95(5): 609-622 (2023) - [c10]Geng-Ming Liang
Support of Sparse Tensor Computing for MLIR HLS. ICPP Workshops 2023: 88-95 - [i1]Ju-Hung Li, Jhih-Kuan Lin, Yung-Cheng Su, Chi-Wei Chu, Lai-Tak Kuok, Hung-Ming Lai, Chao-Lin Lee, Jenq-Kuen Lee:
SIMD Everywhere Optimization from ARM NEON to RISC-V Vector Extensions. CoRR abs/2309.16509 (2023) - 2022
- [j3]Kuan-Hsun Chen
Efficient Realization of Decision Trees for Real-Time Inference. ACM Trans. Embed. Comput. Syst. 21(6): 68:1-68:26 (2022) - [c9]Meng-Shiuan Shih, Hung-Ming Lai, Chao-Lin Lee, Chung-Kai Chen, Jenq-Kuen Lee:
Register-Pressure Aware Predicator for Length Multiplier of RVV. ICPP Workshops 2022: 10:1-10:9 - 2021
- [c8]Che-Chia Lin, Chao-Lin Lee, Jenq-Kuen Lee, Howard Wang, Ming-Yu Hung:
Accelerate Binarized Neural Networks with Processing-in-Memory Enabled by RISC-V Custom Instructions. ICPP Workshops 2021: 15:1-15:8 - [c7]Hui-Hsin Liao, Chao-Lin Lee, Jenq-Kuen Lee, Wei-Chih Lai, Ming-Yu Hung, Chung-Wen Huang:
Support Convolution of CNN with Compression Sparse Matrix Multiplication Flow in TVM. ICPP Workshops 2021: 17:1-17:7 - 2020
- [j2]Chao-Lin Lee, Min-Yih Hsu, Bing-Sung Lu, Ming-Yu Hung, Jenq-Kuen Lee:
Experiment and enabled flow for GPGPU-Sim simulators with fixed-point instructions. J. Syst. Archit. 111: 101783 (2020) - [c6]Chen-Ting Chao, Wei-Hsu Chu, Chao-Lin Lee, Jenq-Kuen Lee, Ming-Yu Hung, Hsiang-Wei Sung:
Devise Sparse Compression Schedulers to Enhance FastText Methods. ICPP Workshops 2020: 4:1-4:8 - [c5]Yi-Ru Chen, Hui-Hsin Liao, Chia-Hsuan Chang, Che-Chia Lin, Chao-Lin Lee, Yuan-Ming Chang, Chun-Chieh Yang, Jenq-Kuen Lee:
Experiments and optimizations for TVM on RISC-V Architectures with P Extension. VLSI-DAT 2020: 1-4
2010 – 2019
- 2019
- [c4]Chao-Lin Lee, Chen-Ting Chao, Jenq-Kuen Lee, Ming-Yu Hung, Chung-Wen Huang:
Accelerate DNN Performance with Sparse Matrix Compression in Halide. ICPP Workshops 2019: 14:1-14:6 - [c3]Chao-Lin Lee, Chen-Ting Chao, Jenq-Kuen Lee, Chung-Wen Huang, Ming-Yu Hung:
Sparse-Matrix Compression Primitives with OpenCL Framework to Support Halide. IWOCL 2019: 24:1-24:2 - 2018
- [j1]Shao-Chung Wang, Li-Chen Kan, Chao-Lin Lee, Yuan-Shin Hwang, Jenq-Kuen Lee:
Architecture and Compiler Support for GPUs Using Energy-Efficient Affine Register Files. ACM Trans. Design Autom. Electr. Syst. 23(2): 18:1-18:25 (2018) - [c2]Chao-Lin Lee, Min-Yih Hsu, Bing-Sung Lu, Jenq-Kuen Lee:
Enable the Flow for GPGPU-Sim Simulators with Fixed-Point Instructions. ICPP Workshops 2018: 12:1-12:5 - 2017
- [c1]Li Wang, Ren-Wei Tsai, Shao-Chung Wang, Kun-Chih Chen
Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator. ISPASS 2017: 127-128
Coauthor Index
aka: Jenq-Kuen Lee
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