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Stephen Adeboye Oyeniran
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2020 – today
- 2022
- [c20]Adeboye Stephen Oyeniran, Maksim Jenihhin, Jaan Raik, Raimund Ubar:
High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test. ISVLSI 2022: 32-37 - 2021
- [c19]Maksim Jenihhin, Adeboye Stephen Oyeniran, Jaan Raik, Raimund Ubar:
Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules. DSD 2021: 557-561 - 2020
- [j1]Adeboye Stephen Oyeniran
, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors. J. Electron. Test. 36(1): 87-103 (2020) - [c18]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors. DSD 2020: 646-650 - [i3]Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar:
New categories of Safe Faults in a processor-based Embedded System. CoRR abs/2009.11621 (2020)
2010 – 2019
- 2019
- [c17]Cemil Cem Gürsoy
New categories of Safe Faults in a processor-based Embedded System. DDECS 2019: 1-4 - [c16]Adeboye Stephen Oyeniran, Raimund Ubar
High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors. ETS 2019: 1-6 - [c15]Lembit Jürimägi
Application Specific True Critical Paths Identification in Sequential Circuits. IOLTS 2019: 299-304 - [c14]Adeboye Stephen Oyeniran, Raimund Ubar
Mixed-level identification of fault redundancy in microprocessors. LATS 2019: 1-6 - [c13]Adeboye Stephen Oyeniran, Raimund Ubar
High-Level Functional Test Generation for Microprocessor Modules. MIXDES 2019: 356-361 - [c12]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
On Test Generation for Microprocessors for Extended Class of Functional Faults. VLSI-SoC (Selected Papers) 2019: 21-44 - [c11]Adeboye Stephen Oyeniran, Raimund Ubar
Implementation-Independent Functional Test Generation for MSC Microprocessors. VLSI-SoC 2019: 82-87 - [i2]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik:
Mixed-level identification of fault redundancy in microprocessors. CoRR abs/1907.12325 (2019) - [i1]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik:
High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors. CoRR abs/1908.02986 (2019) - 2018
- [c10]Adeboye Stephen Oyeniran
Combined pseudo-exhaustive and deterministic testing of array multipliers. AQTR 2018: 1-6 - [c9]Siavoosh Payandeh Azad, Adeboye Stephen Oyeniran
Replication-Based Deterministic Testing of 2-Dimensional Arrays with Highly Interrelated Cells. DDECS 2018: 21-26 - [c8]Adeboye Stephen Oyeniran
Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation. ISCAS 2018: 1-5 - 2017
- [c7]Siavoosh Payandeh Azad, Behrad Niazmand
From online fault detection to fault management in Network-on-Chips: A ground-up approach. DDECS 2017: 48-53 - [c6]Adeboye Stephen Oyeniran
High-level test data generation for software-based self-test in microprocessors. MECO 2017: 1-6 - [c5]Stephen Adeboye Oyeniran
High-level test generation for processing elements in many-core systems. ReCoSoC 2017: 1-8 - 2016
- [c4]Raimund Ubar
Multiple control fault testing in digital systems with high-level decision diagrams. AQTR 2016: 1-6 - [c3]Artjom Jasnetski, Stephen Adeboye Oyeniran
High-level modeling and testing of multiple control faults in digital systems. DDECS 2016: 144-149 - 2015
- [c2]Raimund Ubar
Double Phase Fault Collapsing with Linear Complexity in Digital Circuits. DSD 2015: 700-705 - [c1]Raimund Ubar
Multiple fault testing in systems-on-chip with high-level decision diagrams. IDT 2015: 66-71
Coauthor Index
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