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Vikas Vijayvargiya
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2020 – today
- 2024
- [j5]Aruna Kumari Neelam
, V. Bharath Sreenivasulu
Performance Comparison of Nanosheet FET, CombFET, and TreeFET: Device and Circuit Perspective. IEEE Access 12: 9563-9571 (2024)
2010 – 2019
- 2019
- [j4]Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Nand Kishor Yadav, Santosh Kumar Vishvakarma
An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM. Circuits Syst. Signal Process. 38(4): 1482-1505 (2019) - 2018
- [j3]Pooran Singh
Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design. Integr. 62: 1-13 (2018) - 2017
- [j2]Pooran Singh, Bhupendra Singh Reniwal
Dynamic Feedback Controlled Static Random Access Memory for Low Power Applications. J. Low Power Electron. 13(1): 47-59 (2017) - [c4]Bhupendra Singh Reniwal
A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM. VLSID 2017: 335-340 - 2016
- [j1]Bhupendra Singh Reniwal
Ultra-Fast Current Mode Sense Amplifier for Small \(I_{\mathrm{CELL}}\) SRAM in FinFET with Improved Offset Tolerance. Circuits Syst. Signal Process. 35(9): 3066-3085 (2016) - [c3]Shraddha Thakre, Ankur Beohar, Vikas Vijayvargiya, Nandakishor Yadav
Investigation of DC Characteristic on DG-Tunnel FET with High-K Dielectric Using Distinct Device Parameter. iNIS 2016: 124-128 - 2015
- [c2]Bhupendra Singh Reniwal
Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small Icell SRAM Using FinFET. ACM Great Lakes Symposium on VLSI 2015: 95-98 - [c1]Neha Jagwani, Vikas Vijayvargiya, Santosh Kumar Vishvakarma
Effect of Gate and Channel Engineering on Digital Performance Parameters Using Tied (3T) and Independent (4T) Double Gate MOSFETs. iNIS 2015: 243-247
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