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Alejandro Nocua
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2020 – today
- 2021
- [c7]Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir
, Fatma Jebali, Tanguy Sassolas, Jean-Christophe Weill, Carlos Falquez, Nam Ho, Dirk Pleiter, Antoni Portero
Multilevel simulation-based co-design of next generation HPC microprocessors. PMBS 2021: 18-29 - 2020
- [c6]Alejandro Nocua, Said Derradji, Gregory Vaumourin, Pierre-Axel Lagadec, Zoltan Menyhart:
Mont-Blanc 2020: Simulation Efforts Towards Exascale High Performance Computing : Embedded Tutorial on "DDECS-2020". DDECS 2020: 1-2
2010 – 2019
- 2019
- [j4]Alejandro Nocua
A gem5 trace-driven simulator for fast architecture exploration of OpenMP workloads. Microprocess. Microsystems 67: 42-55 (2019) - 2018
- [c5]David Novo, Alejandro Nocua, Florent Bruguier, Abdoulaye Gamatié, Gilles Sassatelli:
Evaluation of Heterogeneous Multicore Cluster Architectures Designed for Mobile Computing. ReCoSoC 2018: 1-8 - 2017
- [j3]Alejandro Nocua
HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization. J. Circuits Syst. Comput. 26(8): 1740004:1-1740004:19 (2017) - [j2]Alejandro Nocua
A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality. J. Low Power Electron. 13(1): 10-28 (2017) - [c4]Alejandro Nocua, Florent Bruguier
ElasticSimMATE: A fast and accurate gem5 trace-driven simulator for multicore systems. ReCoSoC 2017: 1-8 - 2016
- [c3]Alejandro Nocua
A hybrid power modeling approach to enhance high-level power models. DDECS 2016: 151-156 - [c2]Alejandro Nocua
A Hybrid Power Estimation Technique to improve IP power models quality. VLSI-SoC 2016: 1-6 - 2015
- [j1]Jose Luis Garcia-Gervacio, Alejandro Nocua
Screening small-delay defects using inter-path correlation to reduce reliability risk. Microelectron. Reliab. 55(6): 1005-1011 (2015) - [c1]Alejandro Nocua, Arnaud Virazel
An efficient hybrid power modeling approach for accurate gate-level power estimation. ICM 2015: 17-20
Coauthor Index
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