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Darjn Esposito
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2010 – 2019
- 2019
- [j9]Gerardo Castellano, Davide De Caro, Darjn Esposito
, Paolo Bifulco, Ettore Napoli, Nicola Petra, Emilio Andreozzi
An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy. Circuits Syst. Signal Process. 38(7): 3269-3294 (2019) - [j8]Darjn Esposito
Low-Power Hardware Implementation of Least-Mean-Square Adaptive Filters Using Approximate Arithmetic. Circuits Syst. Signal Process. 38(12): 5606-5622 (2019) - 2018
- [j7]Michele De Martino
A Standard-Cell-Based All-Digital PWM Modulator With High Resolution and Spread- Spectrum Capability. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3885-3896 (2018) - [j6]Darjn Esposito
Approximate Multipliers Based on New Approximate Compressors. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4169-4182 (2018) - [c9]Darjn Esposito, Gennaro Di Meo
Design of Low-Power Approximate LMS Filters with Precision-Scalability. ApplePies 2018: 237-243 - [c8]Darjn Esposito, Gennaro Di Meo
Quality-Scalable Approximate LMS Filter. ICECS 2018: 849-852 - [c7]Antonio G. M. Strollo, Darjn Esposito:
Approximate computing in the nanoscale era. ICICDT 2018: 21-24 - [c6]Darjn Esposito, Gennaro Di Meo
On the Use of Approximate Multipliers in LMS Adaptive Filters. ISCAS 2018: 1-5 - [c5]Darjn Esposito, Gennaro Di Meo
Stall-Aware Fixed-Point Implementation of LMS Filters. PRIME 2018: 169-172 - 2017
- [j5]Ettore Napoli
A SISO Register Circuit Tailored for Input Data with Low Transition Probability. IEEE Trans. Computers 66(1): 45-51 (2017) - [j4]Ettore Napoli
Single Bit Filtering Circuit Implemented in a System for the Generation of Colored Noise. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(5): 1040-1050 (2017) - [j3]Davide De Caro, Ettore Napoli, Darjn Esposito
Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(5): 1187-1200 (2017) - [c4]Darjn Esposito
On the use of approximate adders in carry-save multiplier-accumulators. ISCAS 2017: 1-4 - [c3]Darjn Esposito
Power-precision scalable latch memories. ISCAS 2017: 1-4 - 2016
- [j2]Darjn Esposito
Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8): 1200-1209 (2016) - [c2]Darjn Esposito
Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs. ISCAS 2016: 1970-1973 - [c1]Ettore Napoli, Gerardo Castellano, Darjn Esposito
Digital circuit for the generation of colored noise exploiting single bit pseudo random sequence. LASCAS 2016: 23-26 - 2015
- [j1]Darjn Esposito
Variable Latency Speculative Han-Carlson Adder. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1353-1361 (2015)
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