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Bonan Yan
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2020 – today
- 2024
- [j10]Cenlin Duan
, Jianlei Yang
DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(3): 906-918 (2024) - [j9]Yihan Fu, Daijing Shi, Anjunyi Fan, Wenshuo Yue, Yuchao Yang
Probabilistic Compute-in-Memory Design for Efficient Markov Chain Monte Carlo Sampling. IEEE Trans. Circuits Syst. I Regul. Pap. 71(2): 703-716 (2024) - [c29]Cenlin Duan
Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity. DAC 2024: 209:1-209:6 - [c28]Yihang Zhu, Lei Cai, Lianfeng Yu, Anjunyi Fan, Longhao Yan, Zhaokun Jing, Bonan Yan, Pek Jun Tiw, Yuqi Li, Yaoyu Tao, Yuchao Yang:
MeMCISA: Memristor-Enabled Memory-Centric Instruction-Set Architecture for Database Workloads. MICRO 2024: 1678-1692 - [i7]Rongqing Cong, Wenyang He, Mingxuan Li, Bangning Luo, Zebin Yang, Yuchao Yang, Ru Huang, Bonan Yan:
AttentionLego: An Open-Source Building Block For Spatially-Scalable Large Language Model Accelerator With Processing-In-Memory Technology. CoRR abs/2401.11459 (2024) - [i6]Yifeng Zhai, Bing Li, Bonan Yan, Jing Wang:
STAR: An Efficient Softmax Engine for Attention Model with RRAM Crossbar. CoRR abs/2401.17582 (2024) - [i5]Cenlin Duan, Jianlei Yang, Yiou Wang, Yikun Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao:
Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity. CoRR abs/2404.09497 (2024) - 2023
- [j8]Bonan Yan, Yuchao Yang, Ru Huang:
Memristive dynamics enabled neuromorphic computing systems. Sci. China Inf. Sci. 66(10) (2023) - [j7]Anjunyi Fan, Yihan Fu, Yaoyu Tao, Zhonghua Jin, Haiyue Han, Huiyu Liu, Yaojun Zhang, Bonan Yan
Hadamard product-based in-memory computing design for floating point neural network training. Neuromorph. Comput. Eng. 3(1): 14009 (2023) - [c27]Anjunyi Fan, Bo Hu, Zhonghua Jin, Haiyue Han, Yaojun Zhang, Yue Yang, Yuchao Yang, Bonan Yan, Ru Huang:
Live Demonstration: SRAM Compute-In-Memory Based Visual & Aural Recognition System. AICAS 2023: 1-2 - [c26]Yifeng Zhai, Bing Li, Bonan Yan, Jing Wang:
STAR: An Efficient Softmax Engine for Attention Model with RRAM Crossbar. DATE 2023: 1-2 - [c25]Lei Cai
Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize Search. FPGA 2023: 177-183 - [c24]Yanjun Li
SRAM-Based Processing-In-Memory Design with Kullback-Leibler Divergence-Based Dynamic Precision Quantization. ACM Great Lakes Symposium on VLSI 2023: 189-192 - [i4]Yihan Fu, Daijing Shi, Anjunyi Fan, Wenshuo Yue, Yuchao Yang, Ru Huang, Bonan Yan:
Probabilistic Compute-in-Memory Design For Efficient Markov Chain Monte Carlo Sampling. CoRR abs/2307.10866 (2023) - [i3]Lianfeng Yu, Yaoyu Tao, Teng Zhang, Zeyu Wang, Xile Wang, Zelun Pan, Bowen Wang, Zhaokun Jing, Jiaxin Liu, Yuqi Li, Yihang Zhu, Bonan Yan, Yuchao Yang:
Fast and reconfigurable sort-in-memory system enabled by memristors. CoRR abs/2309.10350 (2023) - [i2]Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao:
DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory. CoRR abs/2310.20424 (2023) - 2022
- [j6]Zhuojian Xiao, Bonan Yan, Teng Zhang, Ru Huang, Yuchao Yang
Memristive devices based hardware for unlabeled data processing. Neuromorph. Comput. Eng. 2(2): 22003 (2022) - [j5]Zhaokun Jing
VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory Accelerators. IEEE Trans. Circuits Syst. I Regul. Pap. 69(10): 4028-4041 (2022) - [c23]Kangyi Qiu, Yaojun Zhang, Bonan Yan, Ru Huang:
Heterogeneous Memory Architecture Accommodating Processing-in-Memory on SoC for AIoT Applications. ASP-DAC 2022: 383-388 - [c22]Ziru Li, Qilin Zheng, Bonan Yan, Ru Huang, Bing Li, Yiran Chen:
ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses. DAC 2022: 1099-1104 - [c21]Bonan Yan, Jeng-Long Hsu, Pang-Cheng Yu, Chia-Chi Lee, Yaojun Zhang, Wenshuo Yue, Guoqiang Mei, Yuchao Yang, Yue Yang, Hai Li, Yiran Chen, Ru Huang:
A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications. ISSCC 2022: 188-190 - 2020
- [b1]Bonan Yan:
Highly Efficient Neuromorphic Computing Systems With Emerging Nonvolatile Memories. Duke University, Durham, NC, USA, 2020 - [c20]Ziru Li, Bonan Yan, Hai Helen Li:
ReSiPE: ReRAM-based Single-Spiking Processing-In-Memory Engine. DAC 2020: 1-6 - [c19]Qilin Zheng, Zongwei Wang, Zishun Feng, Bonan Yan, Yimao Cai, Ru Huang, Yiran Chen, Chia-Lin Yang, Hai Helen Li:
Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks. DAC 2020: 1-6 - [c18]Xiaoxuan Yang
ReTransformer: ReRAM-based Processing-in-Memory Architecture for Transformer Acceleration. ICCAD 2020: 92:1-92:9
2010 – 2019
- 2019
- [j4]Bonan Yan, Bing Li, Ximing Qiao, Cheng-Xin Xue, Meng-Fan Chang, Yiran Chen, Hai Helen Li
Resistive Memory-Based In-Memory Computing: From Device and Large-Scale Integration System Perspectives. Adv. Intell. Syst. 1(7): 1900068 (2019) - [c17]Bing Li, Bonan Yan, Chenchen Liu, Hai (Helen) Li:
Build reliable and efficient neuromorphic design with memristor technology. ASP-DAC 2019: 224-229 - [c16]Bing Li, Bonan Yan, Hai Li:
An Overview of In-memory Processing with Emerging Non-volatile Memory for Data-intensive Applications. ACM Great Lakes Symposium on VLSI 2019: 381-386 - [c15]Arjun Chaudhuri, Bonan Yan, Yiran Chen, Krishnendu Chakrabarty
Hardware Fault Tolerance for Binary RRAM Crossbars. ITC 2019: 1-10 - [i1]Bing Li, Bonan Yan, Hai Li:
An Overview of In-memory Processing with Emerging Non-volatile Memory for Data-intensive Applications. CoRR abs/1906.06603 (2019) - 2018
- [j3]Bonan Yan, Yiran Chen, Hai Li:
Challenges of memristor based neuromorphic computing system. Sci. China Inf. Sci. 61(6): 060425:1-060425:3 (2018) - [c14]Bonan Yan, Xiong Cao, Hai (Helen) Li:
A neuromorphic design using chaotic mott memristor with relaxation oscillation. DAC 2018: 167:1-167:6 - [c13]Bonan Yan, Fan Chen, Yaojun Zhang, Chang Song, Hai Li, Yiran Chen:
Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices. DATE 2018: 109-112 - 2017
- [j2]Enes Eken, Ismail Bayram, Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai (Helen) Li
Giant Spin-Hall assisted STT-RAM and logic design. Integr. 58: 253-261 (2017) - [j1]Yaojun Zhang
Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1181-1192 (2017) - [c12]Shunti Yin, Deepak Kadetotad, Bonan Yan, Chang Song, Yiran Chen, Chaitali Chakrabarti, Jae-sun Seo:
Low-power neuromorphic speech recognition engine with coarse-grain sparsity. ASP-DAC 2017: 111-114 - [c11]Bonan Yan, Jianhua Joshua Yang
A closed-loop design to enhance weight stability of memristor based neural network chips. ICCAD 2017: 541-548 - 2016
- [c10]Bonan Yan, Amr Mahmoud Mahmoud, Jianhua Joshua Yang
A neuromorphic ASIC design using one-selector-one-memristor crossbar. ISCAS 2016: 1390-1393 - [c9]Chenchen Liu, Qing Yang, Bonan Yan, Jianlei Yang, Xiaocong Du, Weijie Zhu, Hao Jiang, Qing Wu, Mark Barnell, Hai Li
A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy. ISVLSI 2016: 110-115 - [c8]Enes Eken, Ismail Bayram, Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai (Helen) Li, Yiran Chen:
Spin-Hall Assisted STT-RAM Design and Discussion. SLIP 2016: 7:1-7:4 - 2015
- [c7]Bonan Yan, Yaojun Zhang, Enes Eken, Wujie Wen, Weisheng Zhao, Yiran Chen:
Recent progresses of STT memory design and applications. ASICON 2015: 1-4 - [c6]Hai (Helen) Li
Spiking-based matrix computation by leveraging memristor crossbar array. CISDA 2015: 1-4 - [c5]Chenchen Liu, Bonan Yan, Chaofei Yang, Linghao Song
A spiking neuromorphic design with resistive crossbar. DAC 2015: 14:1-14:6 - [c4]Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai Li, Yiran Chen:
Giant spin hall effect (GSHE) logic design for low power application. DATE 2015: 1000-1005 - [c3]Bonan Yan, Zheng Li, Yaojun Zhang, Jianlei Yang, Hai Li
A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback. ACM Great Lakes Symposium on VLSI 2015: 69-74 - [c2]Zheng Li, Bonan Yan, Lun Yang, Weisheng Zhao, Yiran Chen, Hai Li
A new self-reference sensing scheme for TLC MRAM. ISCAS 2015: 593-596 - [c1]Zheng Li, Chenchen Liu, Yandan Wang, Bonan Yan, Chaofei Yang, Jianlei Yang, Hai Li:
An overview on memristor crossabr based neuromorphic circuit and architecture. VLSI-SoC 2015: 52-56
Coauthor Index
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last updated on 2024-12-11 21:42 CET by the dblp team
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