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Francisco Rangel-Patino
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2020 – today
- 2020
- [j2]Francisco E. Rangel-Patino
, Andres Viveros-Wacher
A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation. IEEE Trans. Emerg. Top. Comput. 8(2): 453-463 (2020) - [c5]José Ernesto Rayas-Sánchez, Francisco E. Rangel-Patino, Benjamin Mercado-Casillas, Felipe de Jesus Leal-Romo
Machine Learning Techniques and Space Mapping Approaches to Enhance Signal and Power Integrity in High-Speed Links and Power Delivery Networks. LASCAS 2020: 1-4
2010 – 2019
- 2019
- [j1]Francisco E. Rangel-Patino
Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 733-740 (2019) - 2018
- [c4]Francisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Nagib Hakim:
Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation. ITC 2018: 1-10 - [c3]Andres Viveros-Wacher, Ricardo Baca-Baylon, Francisco E. Rangel-Patino, Miguel A. Davalos-Santana, Edgar-Andrei Vega-Ochoa, José Ernesto Rayas-Sánchez:
Jitter tolerance acceleration using the golden section optimization technique. LASCAS 2018: 1-4 - [c2]Francisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Edgar-Andrei Vega-Ochoa, Nagib Hakim:
Direct optimization of a PCI express link equalization in industrial post-silicon validation. LATS 2018: 1-6 - 2014
- [c1]Jesus-Andres Mendoza-Bonilla, Alejandro Cortez-Ibarra, Edgar-Andrei Vega-Ochoa, Francisco Rangel-Patino, Brandon Gore:
Backplane/FDA correlation-FDA replacing commercial backplanes for SoC ethernet electrical validation. VLSI-SoC 2014: 1-6
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