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Zheng Pei Wu

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2010 – 2019

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2016
[j2]
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  - journals/rts/WuPG16
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Zheng Pei Wu, Rodolfo Pellizzoni, Danlu Guo:
A composable worst case latency analysis for multi-rank DRAM devices under open row policy. Real Time Syst. 52(6): 761-807 (2016)
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Gang Yao, Heechul Yun, Zheng Pei Wu, Rodolfo Pellizzoni, Marco Caccamo, Lui Sha:
Schedulability Analysis for Memory Bandwidth Regulated Multicore Real-Time Systems. IEEE Trans. Computers 65(2): 601-614 (2016)
2014
[c3]
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  - conf/ecrts/KrishnapillaiWP14
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Yogen Krishnapillai, Zheng Pei Wu, Rodolfo Pellizzoni:
A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems. ECRTS 2014: 27-38
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Heechul Yun, Renato Mancuso, Zheng Pei Wu, Rodolfo Pellizzoni:
PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms. RTAS 2014: 155-166
2013
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Zheng Pei Wu, Yogen Krish, Rodolfo Pellizzoni:
Worst Case Analysis of DRAM Latency in Multi-requestor Systems. RTSS 2013: 372-383

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