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Jaehoon Yu
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2020 – today
- 2024
- [j21]Junnosuke Suzuki
, Jaehoon Yu
Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision. IEEE Access 12: 2057-2073 (2024) - [j20]Shungo Kumazawa
Toward Improving Ensemble-Based Collaborative Inference at the Edge. IEEE Access 12: 6926-6940 (2024) - [j19]Byeongho Kim
The Breakthrough Memory Solutions for Improved Performance on LLM Inference. IEEE Micro 44(3): 40-48 (2024) - [c33]Masato Watanabe, Shungo Kumazawa, Thiem Van Chu, Kazushi Kawamura, Jaehoon Yu, Masato Motomura:
Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA. ICCE 2024: 1-2 - 2023
- [j18]Jiale Yan
TT-MLP: Tensor Train Decomposition on Deep MLPs. IEEE Access 11: 10398-10411 (2023) - [j17]Ángel López García-Arias
Recurrent Residual Networks Contain Stronger Lottery Tickets. IEEE Access 11: 16588-16604 (2023) - [j16]Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura:
A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems. IEICE Trans. Inf. Syst. 106(12): 1969-1978 (2023) - [c32]Genta Inoue, Daiki Okonogi, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura:
Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance. COOL CHIPS 2023: 1-3 - [c31]Thiem Van Chu, Yu Mizutani, Yuta Nagahara, Shungo Kumazawa, Kazushi Kawamura, Jaehoon Yu, Masato Motomura:
Decision Forest Training Accelerator Based on Binary Feature Decomposition. FCCM 2023: 215 - [c30]Jin Hyun Kim, Yuhwan Ro, Jinin So, Sukhan Lee, Shinhaeng Kang, YeonGon Cho, Hyeonsu Kim, Byeongho Kim, Kyungsoo Kim, Sangsoo Park, Jin-Seong Kim, Sanghoon Cha, Won-Jo Lee, Jin Jung, Jonggeon Lee, Jieun Lee, Joon-Ho Song, Seungwon Lee, Jeonghyeon Cho, Jaehoon Yu, Kyomin Sohn:
Samsung PIM/PNM for Transfmer Based AI : Energy Efficiency on PIM/PNM Cluster. HCS 2023: 1-31 - [c29]Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Arias
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension. ISSCC 2023: 42-43 - [c28]Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura:
A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations. MCSoC 2023: 478-485 - [c27]Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j15]Satoru Jimbo, Daiki Okonogi, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura:
A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers. IEICE Trans. Inf. Syst. 105-D(12): 2019-2031 (2022) - [c26]Yasuyuki Okoshi, Ángel López García-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu:
Multicoated Supermasks Enhance Hidden Networks. ICML 2022: 17045-17055 - [c25]Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura:
APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control. IPDPS Workshops 2022: 414-420 - [c24]Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet. ISSCC 2022: 1-3 - [c23]Masafumi Tanakal, Jaehoon Yu, Masaki Nakagawa, Naoya Tate, Masanori Hashimoto:
Investigating Small Device Implementation of FRET-based Optical Reservoir Computing. MWSCAS 2022: 1-4 - 2021
- [j14]Kazutoshi Hirose
Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture. IEEE Access 9: 6179-6187 (2021) - [j13]Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu:
ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training. Int. J. Netw. Comput. 11(2): 215-230 (2021) - [j12]Junnosuke Suzuki, Tomohiro Kaneko, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu:
ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation. Int. J. Netw. Comput. 11(2): 338-353 (2021) - [c22]Ángel López García-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu:
Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. BMVC 2021: 205 - [c21]Takashi Imagawa, Jaehoon Yu, Masanori Hashimoto
MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA. DATE 2021: 838-843 - [c20]Thiem Van Chu, Ryuichi Kitajima, Kazushi Kawamura, Jaehoon Yu, Masato Motomura:
A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning. FPT 2021: 1-10 - [c19]Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner. HCS 2021: 1-21 - [i2]Ángel López García-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu:
Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. CoRR abs/2111.12330 (2021) - 2020
- [j11]TaiYu Cheng, Yukata Masuda, Jun Chen, Jaehoon Yu
Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training. Integr. 74: 19-31 (2020) - [j10]Ryutaro Doi
Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2572-2587 (2020) - [c18]Kazuki Onishi, Jaehoon Yu, Masanori Hashimoto
Memory Efficient Training using Lookup-Table-based Quantization for Neural Network. AICAS 2020: 251-255 - [c17]Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training. CANDAR 2020: 146-152 - [c16]Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation. CANDAR 2020: 215-220 - [c15]Ángel López García-Arias, Jaehoon Yu
Low-Cost Reservoir Computing using Cellular Automata and Random Forests. ISCAS 2020: 1-5 - [c14]Masanori Hashimoto
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC 2020: 502-504
2010 – 2019
- 2019
- [j9]Salita Sombatsiri, Seiya Shibata, Yuki Kobayashi, Hiroaki Inoue, Takashi Takenaka, Takeo Hosomi, Jaehoon Yu
Parallelism-flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA. IPSJ Trans. Syst. LSI Des. Methodol. 12: 22-37 (2019) - [c13]Toranosuke Tanio, Kouya Takeda, Jaehoon Yu, Masanori Hashimoto
Training Data Reduction using Support Vectors for Neural Networks. APSIPA 2019: 1405-1410 - [c12]Shota Fukui, Jaehoon Yu, Masanori Hashimoto
Distilling Knowledge for Non-Neural Networks. APSIPA 2019: 1411-1416 - [c11]TaiYu Cheng, Jaehoon Yu, Masanori Hashimoto
Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier. PATMOS 2019: 91-96 - 2018
- [j8]Koichi Mitsunari, Jaehoon Yu, Takao Onoye, Masanori Hashimoto
Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(9): 1298-1307 (2018) - [j7]Koichi Mitsunari, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu:
Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(11): 1766-1775 (2018) - [j6]Tomoki Sugiura, Jaehoon Yu, Yoshinori Takeuchi:
Phase Locking Value Calculator Based on Hardware-Oriented Mathematical Expression. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2254-2261 (2018) - [j5]Hiroyuki Ochi
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2723-2736 (2018) - [c10]Koichi Mitsunari, Jaehoon Yu, Masanori Hashimoto
Hardware Architecture for Fast General Object Detection using Aggregated Channel Features. A-SSCC 2018: 55-58 - [c9]Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto
Sneak path free reconfiguration of via-switch crossbars based FPGA. ICCAD 2018: 68 - [c8]Masanori Hashimoto
Interconnect Delay Analysis for RRAM Crossbar Based FPGA. ISVLSI 2018: 522-527 - 2017
- [j4]Yuuka Hirao, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu:
Deformable Part Model Based Arrhythmia Detection Using Time Domain Features. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(11): 2221-2229 (2017) - [j3]Tomoki Sugiura, Masaharu Imai, Jaehoon Yu, Yoshinori Takeuchi:
A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems. J. Inf. Process. 25: 210-219 (2017) - [c7]Tomoki Sugiura, Jaehoon Yu, Yoshinori Takeuchi:
Hardware-oriented algorithm for phase synchronization analysis of biomedical signals. BioCAS 2017: 1-4 - 2016
- [c6]Tomoki Sugiura, Arif Ullah Khan, Jaehoon Yu, Yoshinori Takeuchi, Seiji Kameda, Takatsugu Kamata, Yuki Hayashida
A programmable controller for spatio-temporal pattern stimulation of cortical visual prosthesis. BioCAS 2016: 432-435 - 2015
- [c5]Tomoki Sugiura, Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai:
A low-energy ASIP with flexible exponential Golomb codec for lossless data compression toward artificial vision systems. BioCAS 2015: 1-4 - [c4]Eric Aliwarga, Jaehoon Yu, Masahide Hatanaka, Takao Onoye:
Design of generic hardware for soft cascade-based linear SVM classification. ISPACS 2015: 257-262 - 2014
- [j2]Jaehoon Yu, Ryusuke Miyamoto, Takao Onoye:
Corrections to "A Speed-Up Scheme Based on Multiple-Instance Pruning for Pedestrian Detection Using a Support Vector Machine". IEEE Trans. Image Process. 23(1): 478 (2014) - [c3]Tomoki Sugiura, Shoko Nakatsuka, Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai:
An efficient data compression method for artificial vision systems and its low energy implementation using ASIP technology. BioCAS 2014: 81-84 - [c2]Ryusuke Miyamoto, Jaehoon Yu, Takao Onoye:
Normalized channel features for accurate pedestrian detection. ISCCSP 2014: 582-585 - 2013
- [j1]Jaehoon Yu, Ryusuke Miyamoto, Takao Onoye:
A Speed-Up Scheme Based on Multiple-Instance Pruning for Pedestrian Detection Using a Support Vector Machine. IEEE Trans. Image Process. 22(12): 4752-4761 (2013)
2000 – 2009
- 2007
- [c1]Norihiro Ishikawa
Implementation of AV Streaming System Using Peer-to-Peer Communication. CCNC 2007: 778-782 - 2005
- [i1]B. Abbott, P. Baringer, T. Bolton, Zeno Greenwood, E. Gregores, H. Kim, Chokchai Leangsuksun, D. Meyer, N. Mondal, S. Novaes
Performance of an Operating High Energy Physics Data Grid: DØSAR-Grid. CoRR abs/physics/0501164 (2005)
Coauthor Index
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last updated on 2024-07-24 21:36 CEST by the dblp team
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