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Taehui Na
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2020 – today
- 2023
- [j20]Bayartulga Ishdorj
, Doyeon Kim, Seongmin Ahn, Taehui Na
Offset-Canceling Current-Latched Sense Amplifier With Slow Rise Time Control and Reference Voltage Biasing Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2689-2699 (2023) - [j19]Taehui Na
Ternary Output Binary Neural Network With Zero-Skipping for MRAM-Based Digital In-Memory Computing. IEEE Trans. Circuits Syst. II Express Briefs 70(7): 2655-2659 (2023) - [j18]Bayartulga Ishdorj
Spin-Transfer-Torque Magnetic-Tunnel-Junction-Based Low-Power Nonvolatile Flip-Flop Designs in the Subthreshold Voltage Region. IEEE Trans. Very Large Scale Integr. Syst. 31(10): 1565-1577 (2023) - 2021
- [j17]Taehui Na
STT-MRAM Sensing: A Review. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 12-18 (2021) - [c7]Taehui Na:
Offset Voltage Analysis and Enable Signal Rise Time Control Based Offset Reduction Technique of Current-Latched Sense Amplifier. ICEIC 2021: 1-2 - 2020
- [j16]Taehui Na
Robust Offset-Cancellation Sensing-Circuit-Based Spin-Transfer-Torque Nonvolatile Flip-Flop. IEEE Access 8: 159806-159815 (2020) - [j15]Gwang Hui Choi
Novel MTJ-Based Sensing Inverter Variation Tolerant Nonvolatile Flip-Flop in the Near-Threshold Voltage Region. IEEE Access 8: 191057-191066 (2020)
2010 – 2019
- 2019
- [j14]Taehui Na
Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2548-2555 (2019) - 2018
- [j13]Taehui Na
Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 163-174 (2018) - 2017
- [j12]Taehui Na
Offset-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65 nm CMOS. IEEE J. Solid State Circuits 52(2): 496-504 (2017) - [j11]Byungkyu Song, Taehui Na
A 10T-4MTJ Nonvolatile Ternary CAM Cell for Reliable Search Operation and a Compact Area. IEEE Trans. Circuits Syst. II Express Briefs 64-II(6): 700-704 (2017) - 2016
- [j10]Taehui Na
Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM. IEEE Trans. Circuits Syst. II Express Briefs 63-II(6): 578-582 (2016) - [j9]Taehui Na
An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1361-1370 (2016) - [j8]Sara Choi, Taehui Na
Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. 24(9): 2851-2860 (2016) - [j7]Taehui Na
Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. 24(9): 2993-2997 (2016) - [c6]Sara Choi, Taehui Na
Area-optimal sensing circuit designs in deep submicrometer STT-RAM. ISCAS 2016: 1246-1249 - [c5]Beomsang Yoo, Taehui Na
Equalization scheme analysis for high-density spin transfer torque random access memory. ISOCC 2016: 99-100 - 2015
- [j6]Byungkyu Song, Taehui Na
Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(7): 1776-1784 (2015) - [j5]Taehui Na
A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory. IEEE Trans. Circuits Syst. II Express Briefs 62-II(12): 1109-1113 (2015) - [c4]Taehui Na
Efficiency analysis of importance sampling in deep submicron STT-RAM design using uncontrollable industry-compatible model parameter. ICECS 2015: 400-403 - [c3]Byungkyu Song, Taehui Na
Reference-circuit analysis for high-bandwidth spin transfer torque random access memory. ISLPED 2015: 365-370 - 2014
- [j4]Jisu Kim, Taehui Na
A Split-Path Sensing Circuit for Spin Torque Transfer MRAM. IEEE Trans. Circuits Syst. II Express Briefs 61-II(3): 193-197 (2014) - [j3]Taehui Na
Reference-Scheme Study and Novel Reference Scheme for Deep Submicrometer STT-RAM. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3376-3385 (2014) - [j2]Taehui Na
Comparative Study of Various Latch-Type Sense Amplifiers. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 425-429 (2014) - [j1]Taehui Na
An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1620-1624 (2014) - [c2]Taehui Na
High-performance low-power magnetic tunnel junction based non-volatile flip-flop. ISCAS 2014: 1953-1956 - 2013
- [c1]Taehui Na
A comparative study of STT-MTJ based non-volatile flip-flops. ISCAS 2013: 109-112
Coauthor Index
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