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Sabyasachee Banerjee
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2020 – today
- 2024
- [j3]Sabyasachee Banerjee
, Subhashis Majumder, Bhargab B. Bhattacharya, Debesh K. Das:
Power-aware partitioning and test time reduction for 3D-SoC. Innov. Syst. Softw. Eng. 20(3): 485-498 (2024) - [c10]Sabyasachee Banerjee
On Managing Test-Time, Power, and Layer Assignment in 3D SoCs with Built-In-Self-Repair Modules. VLSID 2024: 684-689 - 2021
- [j2]Sabyasachee Banerjee
Fast algorithms for test optimization of core based 3D SoC. Integr. 77: 70-88 (2021) - [j1]Sabyasachee Banerjee
Designing balanced wrapper chains in 3D SoC under constrained TSVs. Innov. Syst. Softw. Eng. 17(3): 219-230 (2021) - 2020
- [d1]Sabyasachee Banerjee:
Experimental result of our BISR work. IEEE DataPort, 2020
2010 – 2019
- 2019
- [c9]Soumendu Ghorui, Sabyasachee Banerjee
A Deterministic Multi-layered Partitioning Tool for Wire-Length Reduction of Monolithic 3D-IC. HiPC 2019: 44-51 - 2018
- [c8]Sabyasachee Banerjee
Test-Time Reduction for Power-Aware 3D-SoC. VLSID 2018: 103-108 - 2017
- [c7]Sabyasachee Banerjee
A placement optimization technique for 3D IC. ISED 2017: 1-5 - 2016
- [c6]Sabyasachee Banerjee
Power-aware test optimization for core-based 3D-SOCs under TSV-constraints. VLSI-SoC 2016: 1-6 - 2015
- [c5]Sabyasachee Banerjee
Partitioning-based test time reduction for core-based 3DICs. VDAT 2015: 1-5 - 2014
- [c4]Adnaan Ahmed, Nitesh Agarwal, Sabyasachee Banerjee
Image steganography by closest pixel-pair mapping. ICACCI 2014: 1971-1975 - [c3]Sabyasachee Banerjee
A Graph-Based 3D IC Partitioning Technique. ISVLSI 2014: 613-618 - [c2]Sabyasachee Banerjee
A thermal aware 3D IC partitioning technique. VDAT 2014: 1-6 - 2012
- [c1]Prasun Ghosal, Arijit Chakraborty, Sabyasachee Banerjee
Honey Bee Based Vehicular Traffic Optimization and Management. BIC-TA (2) 2012: 455-463 - [i1]Prasun Ghosal, Arijit Chakraborty, Sabyasachee Banerjee, Satabdi Barman:
Speed Optimization In Unplanned Traffic Using Bio-Inspired Computing And Population Knowledge Base. CoRR abs/1212.2866 (2012)
Coauthor Index
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