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Woo-Cheol Kwon
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2010 – 2019
- 2018
- [b1]Woo-Cheol Kwon:
Co-design of on-chip caches and networks for scalable shared-memory many-core CMPs. Massachusetts Institute of Technology, Cambridge, USA, 2018 - 2015
- [c11]Woo-Cheol Kwon, Li-Shiuan Peh:
A universal ordered NoC design platform for shared-memory MPSoC. ICCAD 2015: 697-704 - 2014
- [j3]Tushar Krishna, Chia-Hsin Owen Chen, Woo-Cheol Kwon, Li-Shiuan Peh:
Smart: Single-Cycle Multihop Traversals over a Shared Network on Chip. IEEE Micro 34(3): 43-56 (2014) - [c10]Woo-Cheol Kwon, Tushar Krishna, Li-Shiuan Peh:
Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs. ASPLOS 2014: 715-728 - [c9]Chia-Hsin Owen Chen, Sunghyun Park, Suvinay Subramanian, Tushar Krishna, Bhavya K. Daya, Woo-Cheol Kwon, Brett Wilkerson, John Arends, Anantha P. Chandrakasan, Li-Shiuan Peh:
SCORPIO: 36-core shared memory processor demonstrating snoopy coherence on a mesh interconnect. Hot Chips Symposium 2014: 1-20 - [c8]Bhavya K. Daya, Chia-Hsin Owen Chen, Suvinay Subramanian, Woo-Cheol Kwon, Sunghyun Park, Tushar Krishna, Jim Holt, Anantha P. Chandrakasan, Li-Shiuan Peh:
SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering. ISCA 2014: 25-36 - 2013
- [j2]Tushar Krishna, Chia-Hsin Owen Chen, Sunghyun Park, Woo-Cheol Kwon, Suvinay Subramanian, Anantha P. Chandrakasan, Li-Shiuan Peh:
Single-Cycle Multihop Asynchronous Repeated Traversal: A SMART Future for Reconfigurable On-Chip Networks. Computer 46(10): 48-55 (2013) - [c7]Tushar Krishna, Chia-Hsin Owen Chen, Woo-Cheol Kwon, Li-Shiuan Peh:
Breaking the on-chip latency barrier using SMART. HPCA 2013: 378-389
2000 – 2009
- 2009
- [c6]Woo-Cheol Kwon, Sungjoo Yoo, Junhyung Um, Seh-Woong Jeong:
In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem. DATE 2009: 1058-1063 - 2008
- [c5]Woo-Cheol Kwon, Sungjoo Yoo, Sung-Min Hong, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo:
A practical approach of memory access parallelization to exploit multiple off-chip DDR memories. DAC 2008: 447-452 - [c4]Woo-Cheol Kwon, Sung-Min Hong, Sungjoo Yoo, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo:
An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication. DATE 2008: 1244-1249 - 2006
- [c3]Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-Taek Kim, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, Taewhan Kim:
A systematic IP and bus subsystem modeling for platform-based system design. DATE 2006: 560-564 - 2005
- [j1]Woo-Cheol Kwon, Taewhan Kim:
Optimal voltage allocation techniques for dynamically variable voltage processors. ACM Trans. Embed. Comput. Syst. 4(1): 211-230 (2005) - 2003
- [c2]Woo-Cheol Kwon, Taewhan Kim:
Optimal voltage allocation techniques for dynamically variable voltage processors. DAC 2003: 125-130 - 2000
- [c1]Jae-Ha Lee, Otfried Cheong, Woo-Cheol Kwon, Sung Yong Shin, Kyung-Yong Chwa:
Approximation of Curvature-Constrained Shortest Paths through a Sequence of Points. ESA 2000: 314-325
Coauthor Index
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