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Steffen Köhler
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2010 – 2019
- 2017
- [c16]Oliver Knodel
, Steffen Köhler, Marko Rößler, Rainer G. Spallek:
First Workshop on Hardware Defined Programming - HDP. GI-Jahrestagung 2017: 467-468 - [c15]Steffen Köhler, Rainer G. Spallek:
Modellierung anwendungsspezifischer Hardware und deren Einbettung in die DBT-basierte Prozessor-Verhaltenssimulation. GI-Jahrestagung 2017: 493-501 - 2014
- [c14]Laura Bresser, Steffen Köhler, Christoph Schwaab:
The Development of an Application for Data Privacy by Applying an Audit Repository based on IHE ATNA. eHealth 2014: 219-225 - 2013
- [c13]Patrick Lehmann, Thomas Frank, Oliver Knodel
Weasel: A platform-independent streaming-optimized SATA controller. FPL 2013: 1-4
2000 – 2009
- 2009
- [b1]Steffen Köhler:
Parallelität und dynamische Datenpfadrekonfiguration in eingebetteten RISC-Prozessoren. Dresden University of Technology, 2009, pp. 1-149 - 2008
- [c12]Steffen Köhler, Jan Schirok, Jens Braunes, Rainer G. Spallek:
Efficiency of Dynamic Reconfigurable Datapath Extensions -- A Case Study. ARC 2008: 296-301 - 2006
- [c11]Steffen Köhler, Martin Zimmerling, Martin Zabel, Rainer G. Spallek:
Prototyping and Application Development Framework for Dynamically Reconfigurable DSP Architectures. ARCS Workshops 2006: 142-151 - 2005
- [c10]Jens Braunes, Steffen Köhler, Annett Königsmann, Rainer G. Spallek:
Ein Zwischenformat-Profiler für das RECAST-Framework. ARCS Workshops 2005: 33-38 - [c9]Martin Zabel, Steffen Köhler, Martin Zimmerling, Thomas B. Preußer, Rainer G. Spallek:
Design space exploration of coarse-grain reconfigurable DSPs. ReConFig 2005 - 2004
- [c8]Jens Braunes, Steffen Köhler, Rainer G. Spallek:
RECAST: An Evaluation Framework for Coarse-Grain Reconfigurable Architectures. ARCS 2004: 156-166 - [c7]Thomas Preußer, Steffen Köhler, Rainer G. Spallek:
RECAST - Design Space Exploration for Dynamic Reconfigurable Embedded Computing. ESA/VLSI 2004: 130-135 - [c6]Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek:
Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration. FPL 2004: 781-790 - 2002
- [c5]Sebastian Friebe, Steffen Köhler, Rainer G. Spallek, Henrik Juhr, Klaus Künanz:
A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor. FPL 2002: 1164-1167 - [c4]Steffen Köhler, Jens Braunes, Sergej Sawitzki, Rainer G. Spallek:
Improving Code Efficiency for Reconfigurable VLIW Processors. IPDPS 2002 - 2001
- [c3]Sergej Sawitzki, Steffen Köhler, Rainer G. Spallek:
Prototyping Framework for Reconfigurable Processors. FPL 2001: 6-16 - 2000
- [c2]Sergej Sawitzki, Steffen Köhler, Rainer G. Spallek, Jörg Schneider, S. Rülke:
Experimenteller Vergleich verschiedener Entwurfsmethoden für FPGA-basierte Entwurfsabläufe. MBMV 2000: 236-244
1990 – 1999
- 1999
- [c1]Steffen Köhler, Sergej Sawitzki, Achim Gratz, Rainer G. Spallek:
Digital Signal Processing with General Purpose Microprocessors, DSP and Rcinfigurable Logic. IPPS/SPDP Workshops 1999: 706-708
Coauthor Index
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