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John D. Leidel
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2020 – today
- 2024
- [c35]John D. Leidel
, David Donofrio
Scaling SST for Extreme Scale System Simulation. CF (Companion) 2024 - [c34]Jie Li, John D. Leidel
Towards Cycle-accurate Simulation of xBGAS. ICNC 2024: 468-472 - [i2]Patrick Diehl, Gregor Daiß, Steven R. Brandt, Alireza Kheirkhahan, Srinivas Yadav Singanaboina, Dominic Marcello, Chris Taylor, John Leidel, Hartmut Kaiser:
Distributed astrophysics simulations using Octo-Tiger with RISC-V CPUs using HPX and Kokkos. CoRR abs/2407.00026 (2024) - 2023
- [c33]John D. Leidel
Application Level Architecture Design. CF 2023: 351 - [c32]Mert Side, Brody Williams, John D. Leidel, Jonathan Woodruff, Simon W. Moore, Yong Chen:
Towards xBGAS on CHERI: Supporting a Secure Global Memory. IPDPS Workshops 2023: 578-581 - [c31]Patrick Diehl
Evaluating HPX and Kokkos on RISC-V using an astrophysics application Octo-Tiger. SC Workshops 2023: 1533-1542 - [i1]Patrick Diehl, Gregor Daiß, Steven R. Brandt, Alireza Kheirkhahan, Hartmut Kaiser, Christopher Taylor, John Leidel:
Evaluating HPX and Kokkos on RISC-V using an Astrophysics Application Octo-Tiger. CoRR abs/2309.06530 (2023) - 2022
- [c30]Michael Beebe, Brody Williams, Stephen Devaney, John D. Leidel, Yong Chen, Steve Poole:
RaiderSTREAM: Adapting the STREAM Benchmark to Modern HPC Systems. HPEC 2022: 1-7 - 2021
- [j5]Xi Wang
HAM: Hotspot-Aware Manager for Improving Communications With 3D-Stacked Memory. IEEE Trans. Computers 70(6): 833-848 (2021) - [c29]Zach Hansen
DMM-GAPBS: Adapting the GAP Benchmark Suite to a Distributed Memory Model. HPEC 2021: 1-8 - [c28]Ryan Kabrick, John D. Leidel, David Donofrio:
Toward HDL Extensions for Rapid AI/ML Accelerator Generation. HPEC 2021: 1-6 - [c27]Xi Wang, John D. Leidel
xBGAS: A Global Address Space Extension on RISC-V for High Performance Computing. IPDPS 2021: 454-463 - [c26]John D. Leidel, Ryan Kabrick, David Donofrio:
Toward an Automated Hardware Pipelining LLVM Pass Infrastructure. LLVM-HPC@SC 2021: 39-49 - [c25]Brody Williams, John D. Leidel, Xi Wang, David Donofrio, Yong Chen:
CircusTent: A Tool for Measuring the Performance of Atomic Memory Operations on Emerging Architectures. OpenSHMEM 2021: 92-110 - 2020
- [j4]John D. Leidel
Toward a Microarchitecture for Efficient Execution of Irregular Applications. ACM Trans. Parallel Comput. 7(4): 26:1-26:24 (2020) - [c24]John D. Leidel, David Donofrio, Frank Conlon:
StoneCutter: a very high level instruction set design language. CF 2020: 233-236 - [c23]Xi Wang, Brody Williams, John D. Leidel, Alan Ehret, Michel A. Kinsy, Yong Chen:
Remote Atomic Extension (RAE) for Scalable High Performance Computing. DAC 2020: 1-6 - [c22]Xi Wang, John D. Leidel, Brody Williams, Yong Chen
PAC: Paged Adaptive Coalescer for 3D-Stacked Memory. HPDC 2020: 137-148 - [c21]Brody Williams, John D. Leidel, Xi Wang, David Donofrio, Yong Chen:
CircusTent: A Benchmark Suite for Atomic Memory Operations. MEMSYS 2020: 144-157
2010 – 2019
- 2019
- [c20]Xi Wang, Jie Li, Antonino Tumeo, John D. Leidel, Yong Chen:
POSTER: Memory Hotspot Optimization for Data-Intensive Applications. PACT 2019: 467-468 - [c19]John D. Leidel, Frank Conlon:
Toward a graph-based dependence analysis framework for high level design verification. CF 2019: 308-316 - [c18]Xi Wang, Antonino Tumeo, John D. Leidel, Jie Li
MAC: Memory Access Coalescer for 3D-Stacked Memory. ICPP 2019: 2:1-2:10 - [c17]Brody Williams, Xi Wang, John D. Leidel, Yong Chen
Collective Communication for the RISC-V xBGAS ISA Extension. ICPP Workshops 2019: 17:1-17:10 - [c16]Jie Li
PIMS: a lightweight processing-in-memory accelerator for stencil computations. MEMSYS 2019: 41-52 - 2018
- [c15]John D. Leidel, Xi Wang, Yong Chen
GoblinCore-64: A RISC-V Based Architecture for Data Intensive Computing. HPEC 2018: 1-8 - [c14]Xi Wang, John D. Leidel, Yong Chen
Memory Coalescing for Hybrid Memory Cube. ICPP 2018: 62:1-62:10 - [c13]John D. Leidel:
Stake: a coupled simulation environment for RISC-V memory experiments. MEMSYS 2018: 365-376 - [c12]John D. Leidel, Xi Wang, Frank Conlon, Yong Chen
xBGAS: Toward a RISC-V ISA Extension for Global, Scalable Shared Memory. MCHPC@SC 2018: 22-26 - 2017
- [b1]John D. Leidel:
GoblinCore-64: A scalable, open architecture for data intensive high performance computing. Texas Tech University, Lubbock, USA, 2017 - [j3]Tim Finkbeiner, Glen Hush, Troy Larsen, Perry Lea, John D. Leidel, Troy Manning:
In-Memory Intelligence. IEEE Micro 37(4): 30-38 (2017) - [j2]John D. Leidel, Yong Chen
HMC-Sim-2.0: A co-design infrastructure for exploring custom memory cube operations. Parallel Comput. 68: 77-88 (2017) - [c11]Farzad Fatollahi-Fard, David Donofrio, John Shalf
OpenSoC system architect: An open toolkit for building soft-cores on FPGAs. FPL 2017: 1 - [c10]Xi Wang, John D. Leidel, Yong Chen
OpenMP Memkind: An Extension for Heterogeneous Physical Memories. ICPP Workshops 2017: 220-227 - [c9]John D. Leidel, Xi Wang, Yong Chen
Pressure-Driven Hardware Managed Thread Concurrency for Irregular Applications. IA3@SC 2017: 7:1-7:8 - [c8]John D. Leidel:
Bit Contiguous Memory Allocation for Processing In Memory. MCHPC@SC 2017: 11-19 - 2016
- [c7]John D. Leidel, Yong Chen
HMC-Sim-2.0: A Simulation Platform for Exploring Custom Memory Cube Operations. IPDPS Workshops 2016: 621-630 - [c6]John D. Leidel, Yong Chen
Exploring Tag-Bit Memory Operations in Hybrid Memory Cubes. MEMSYS 2016: 153-163 - [c5]Xi Wang, John D. Leidel, Yong Chen
Concurrent Dynamic Memory Coalescing on GoblinCore-64 Architecture. MEMSYS 2016: 177-187 - 2015
- [c4]John D. Leidel, Yong Chen
Communication Avoiding Power Scaling. ICPP Workshops 2015: 166-174 - 2014
- [j1]John D. Leidel, Yong Chen
HMC-SIM: A Simulation Framework for Hybrid Memory Cube Devices. Parallel Process. Lett. 24(4) (2014) - [c3]John D. Leidel, Yong Chen
HMC-Sim: A Simulation Framework for Hybrid Memory Cube Devices. IPDPS Workshops 2014: 1465-1474 - 2013
- [c2]John D. Leidel, Joe Bolding, Geoffrey Rogers:
Toward a Scalable Heterogeneous Runtime System for the Convey MX Architecture. IPDPS Workshops 2013: 1597-1606 - 2012
- [c1]John D. Leidel, Kevin Wadleigh, Joe Bolding, Tony Brewer, Dean Walker:
CHOMP: A Framework and Instruction Set for Latency Tolerant, Massively Multithreaded Processors. SC Companion 2012: 232-239
Coauthor Index
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