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Alexandra Ferreron
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- affiliation: University of Zaragoza, Spain
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2010 – 2019
- 2019
- [j3]Alexandra Ferrerón-Labari, Jesús Alastruey-Benedé
, Darío Suárez Gracia
A fault-tolerant last level cache for CMPs operating at ultra-low voltage. J. Parallel Distributed Comput. 125: 31-44 (2019) - 2018
- [i2]Alexandra Ferreron, Jesús Alastruey-Benedé, Darío Suárez Gracia, Ulya R. Karpuzcu:
AISC: Approximate Instruction Set Computer. CoRR abs/1803.06955 (2018) - [i1]Alexandra Ferreron, Radhika Jagtap, Sascha Bischoff, Roxana Rusitoru:
Crossing the Architectural Barrier: Evaluating Representative Regions of Parallel HPC Applications. CoRR abs/1803.09584 (2018) - 2017
- [c5]Alexandra Ferreron, Radhika Jagtap, Sascha Bischoff, Roxana Rusitoru:
Crossing the architectural barrier: Evaluating representative regions of parallel HPC applications. ISPASS 2017: 109-120 - 2016
- [j2]Alexandra Ferrerón-Labari
Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage. IEEE Trans. Computers 65(3): 755-769 (2016) - [c4]Alexandra Ferreron, Radhika Jagtap, Roxana Rusitoru:
Identifying representative regions of parallel HPC applications: a cross-architectural evaluation. IISWC 2016: 223-224 - 2014
- [j1]Darío Suárez Gracia, Alexandra Ferrerón-Labari, Luis Montesano Del Campo, Teresa Monreal Arnal, Víctor Viñals Yúfera
Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping. ACM Trans. Archit. Code Optim. 11(2): 19:1-19:26 (2014) - [c3]Alexandra Ferrerón-Labari, Darío Suárez Gracia
Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages. SBAC-PAD 2014: 238-245 - 2013
- [c2]Alexandra Ferrerón-Labari, Marta Ortín-Obón
Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors. ARCS 2013: 256-267 - [c1]Marta Ortín
Characterization and cost-efficient selection of NoC topologies for general purpose CMPs. INA-OCMC@HiPEAC 2013: 21-24
Coauthor Index
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