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Olivier Potin
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2020 – today
- 2024
- [j6]Louis Noyez
, Nadia El Mrabet
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E2. ACM Trans. Reconfigurable Technol. Syst. 17(1): 9:1-9:31 (2024) - [c18]Côme Allart
Using a Performance Model to Implement a Superscalar CVA6. CF (Companion) 2024 - [i4]Côme Allart, Jean-Roch Coulon, André Sintzoff, Olivier Potin, Jean-Baptiste Rigaud:
Using a Performance Model to Implement a Superscalar CVA6. CoRR abs/2410.01442 (2024) - 2023
- [j5]Anthony Zgheib
Experimental EMFI detection on a RISC-V core using the Trace Verifier solution. Microprocess. Microsystems 103: 104968 (2023) - [c17]Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud
A CCFI Verification Scheme Based on the RISC-V Trace Encoder. COSADE 2023: 42-61 - [c16]Nathan Roussel, Olivier Potin, Jean-Max Dutertre, Jean-Baptiste Rigaud:
Security Evaluation of a Hybrid CMOS/MRAM Ascon Hardware Implementation. DATE 2023: 1-6 - [c15]François Bonnal, Vincent Dupaquis, Olivier Potin, Jean-Max Dutertre:
Software-Only Control-Flow Integrity Against Fault Injection Attacks. DSD 2023: 269-277 - [c14]Clément Gaine, Pierre-Alain Moëllic, Olivier Potin, Jean-Max Dutertre:
Fault Injection on Embedded Neural Networks: Impact of a Single Instruction Skip. DSD 2023: 317-324 - [c13]Théophile Gousselot, Olivier Thomas, Jean-Max Dutertre, Olivier Potin, Jean-Baptiste Rigaud
Lightweight Countermeasures Against Original Linear Code Extraction Attacks on a RISC-V Core. HOST 2023: 89-99 - [c12]Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud, Jean-Max Dutertre:
CIFER: Code Integrity and control Flow verification for programs Executed on a RISC-V core. HOST 2023: 100-110 - [i3]Clément Gaine, Pierre-Alain Moëllic, Olivier Potin, Jean-Max Dutertre:
Fault Injection on Embedded Neural Networks: Impact of a Single Instruction Skip. CoRR abs/2308.16665 (2023) - 2022
- [c11]Clément Fanjas, Clément Gaine, Driss Aboulkassimi, Simon Pontié, Olivier Potin:
Combined Fault Injection and Real-Time Side-Channel Analysis for Android Secure-Boot Bypassing. CARDIS 2022: 25-44 - [c10]Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud
A CFI Verification System based on the RISC-V Instruction Trace Encoder. DSD 2022: 456-463 - [c9]Nathan Roussel, Olivier Potin, Gregory di Pendina, Jean-Max Dutertre, Jean-Baptiste Rigaud
CMOS/STT-MRAM Based Ascon LWC: a Power Efficient Hardware Implementation. ICECS 2022 2022: 1-4 - [i2]Clément Fanjas, Clément Gaine, Driss Aboulkassimi, Simon Pontié, Olivier Potin:
Real-Time Frequency Detection to Synchronize Fault Injection on System-on-Chip. IACR Cryptol. ePrint Arch. 2022: 602 (2022) - 2020
- [c8]Alexandre Menu, Jean-Max Dutertre, Olivier Potin, Jean-Baptiste Rigaud
Experimental Analysis of the Electromagnetic Instruction Skip Fault Model. DTIS 2020: 1-7
2010 – 2019
- 2019
- [c7]Jean-Max Dutertre, Timothée Riom, Olivier Potin, Jean-Baptiste Rigaud
Experimental Analysis of the Laser-Induced Instruction Skip Fault Model. NordSec 2019: 221-237 - 2018
- [j4]Raphael Andreoni Camponogara Viera
Assessing body built-in current sensors for detection of multiple transient faults. Microelectron. Reliab. 88-90: 128-134 (2018) - [c6]Damien Couroussé, Thierno Barry, Bruno Robisson
All paths lead to Rome: Polymorphic Runtime Code Generation for Embedded Systems. CS2@HiPEAC 2018: 17-18 - 2017
- [c5]Karim M. Abdellatif, Damien Couroussé, Olivier Potin, Philippe Jaillon:
Filtering-based CPA: a successful side-channel attack against desynchronization countermeasures. CS2@HiPEAC 2017: 29-32 - [i1]Damien Couroussé, Thierno Barry, Bruno Robisson, Philippe Jaillon, Olivier Potin, Jean-Louis Lanet:
Runtime Code Polymorphism as a Protection Against Side Channel Attacks. IACR Cryptol. ePrint Arch. 2017: 699 (2017) - 2016
- [c4]Damien Couroussé
Runtime Code Polymorphism as a Protection Against Side Channel Attacks. WISTP 2016: 136-152 - 2014
- [j3]Jean-Max Dutertre
Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS. Microelectron. Reliab. 54(9-10): 2289-2294 (2014) - 2013
- [j2]Vincent Kerzerho, Serge Bernard
A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC. Microelectron. J. 44(9): 840-843 (2013) - [j1]Jean-Max Dutertre
Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection. Microelectron. Reliab. 53(9-11): 1320-1324 (2013) - [c3]Haithem Ayari, Florence Azaïs, Serge Bernard
Implementing model redundancy in predictive alternate test to improve test confidence. ETS 2013: 1 - 2012
- [c2]Haithem Ayari, Florence Azaïs, Serge Bernard
Making predictive analog/RF alternate test strategy independent of training set size. ITC 2012: 1-9 - [c1]Haithem Ayari, Florence Azaïs, Serge Bernard
Smart selection of indirect parameters for DC-based alternate RF IC testing. VTS 2012: 19-24
Coauthor Index
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