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Piet Engelke
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2020 – today
- 2020
- [c30]Manu Baby, Bernd Büttner, Piet Engelke, Ulrike Pfannkuchen, Reinhard Meier, Jonathan Gaudet, Jean-François Côté, Givargis Danialy, Martin Keim, Lori Schramm:
IJTAG Through a Two-Pin Chip Interface. ITC 2020: 1-5
2010 – 2019
- 2017
- [c29]Artur Jutman
, Christophe Lotz, Erik Larsson
BASTION: Board and SoC test instrumentation for ageing and no failure found. DATE 2017: 115-120 - 2014
- [c28]Piet Engelke:
Struktureller Test im System. Aspekte der Technischen Informatik 2014: 5-10 - [c27]Felix Reimann, Michael Glaß
Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures. DAC 2014: 96:1-96:9 - [c26]Ulrich Abelein, Alejandro Cook, Piet Engelke, Michael Glaß, Felix Reimann, Laura Rodríguez Gómez, Thomas Russ, Jürgen Teich, Dominik Ull, Hans-Joachim Wunderlich:
Non-intrusive integration of advanced diagnosis features in automotive E/E-architectures. DATE 2014: 1-6 - 2013
- [c25]Tobias Koal, Markus Ulbricht, Piet Engelke, Heinrich Theodor Vierhaus:
On the feasibility of combining on-line-test and self repair for logic circuits. DDECS 2013: 187-192 - 2012
- [c24]Christian Gleichner, Heinrich Theodor Vierhaus, Piet Engelke:
Scan Based Tests via Standard Interfaces. DSD 2012: 844-851 - [c23]Piet Engelke, Hermann Obermeir:
Funding project DIANA - Integrated diagnostics for the analysis of electronic failures in vehicles. ETS 2012: 1 - 2010
- [j7]Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. Int. J. Parallel Program. 38(3-4): 185-202 (2010)
2000 – 2009
- 2009
- [b1]Piet Engelke:
Resistive bridging faults - defect-oriented modeling and efficient testing (Resistive bridging faults - defektorientierte Modellierung und effizienter Test). University of Freiburg, Germany, 2009 - [j6]Piet Engelke, Bernd Becker
SUPERB: Simulator utilizing parallel evaluation of resistive bridges. ACM Trans. Design Autom. Electr. Syst. 14(4): 56:1-56:21 (2009) - [c22]Alejandro Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
Dynamic Compaction in SAT-Based ATPG. Asian Test Symposium 2009: 187-190 - [c21]Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. VLSI Design 2009: 227-232 - [c20]Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker
An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. VTS 2009: 21-26 - 2008
- [j5]Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2): 327-338 (2008) - [c19]Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker
Resistive Bridging Fault Simulation of Industrial Circuits. DATE 2008: 628-633 - [c18]Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker
Diagnosis of Realistic Defects Based on the X-Fault Model. DDECS 2008: 263-266 - [c17]Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker
A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. ETS 2008: 113-118 - [c16]Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker
Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. ITC 2008: 1-10 - [c15]Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker
Automatic Test Pattern Generation for Interconnect Open Defects. VTS 2008: 181-186 - 2007
- [c14]Stefan Spinner, Jie Jiang, Ilia Polian, Piet Engelke, Bernd Becker:
Simulating Open-Via Defects. ATS 2007: 265-270 - [c13]Piet Engelke, Bettina Braitling, Ilia Polian, Michel Renovell, Bernd Becker:
SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges. ATS 2007: 433-438 - 2006
- [j4]Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker:
Automatic Test Pattern Generation for Resistive Bridging Faults. J. Electron. Test. 22(1): 61-69 (2006) - [j3]Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
Simulating Resistive-Bridging and Stuck-At Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2181-2192 (2006) - [j2]Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker
X-masking during logic BIST and its impact on defect coverage. IEEE Trans. Very Large Scale Integr. Syst. 14(2): 193-202 (2006) - [c12]Piet Engelke, Ilia Polian, Hans Manhaeve, Michel Renovell, Bernd Becker
Delta-IDDQ Testing of Resistive Short Defects. ATS 2006: 63-68 - [c11]Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker
A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency. ATS 2006: 273-278 - 2005
- [j1]Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
Modeling Feedback Bridging Faults with Non-Zero Resistance. J. Electron. Test. 21(1): 57-69 (2005) - [c10]Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Asian Test Symposium 2005: 266-271 - [c9]Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker
A unified fault model and test generation procedure for interconnect opens and bridges. ETS 2005: 22-27 - [c8]Ilia Polian, Sandip Kundu, Jean-Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. VTS 2005: 343-348 - 2004
- [c7]Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
Automatic test pattern generation for resistive bridging faults. ETS 2004: 160-165 - [c6]Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker:
X-Masking During Logic BIST and Its Impact on Defect Coverage. ITC 2004: 442-451 - [c5]Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. VTS 2004: 171-178 - 2003
- [c4]Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
Modeling feedback bridging faults with non-zero resistance. ETW 2003: 91-96 - [c3]Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker:
Simulating Resistive Bridging and Stuck-At Faults. ITC 2003: 1051-1059 - 2002
- [c2]Ilia Polian, Piet Engelke, Bernd Becker:
Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics. ISMVL 2002: 216-223 - 2000
- [c1]Piet Engelke, Bernd Becker, Martin Keim:
A parameterizable fault simulator for bridging faults. ETW 2000: 63-68
Coauthor Index
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