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S. Mahapatra

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This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.

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2010 – 2019

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2018
[c5]
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K. R. Khiangte Amlta, A. Laha, S. Mahapatra, U. Gangway:
Epitaxial Gd2O3on Si (111) Substrate by Sputtering to Enable Low Cost SOI. DRC 2018: 1-2
[c4]
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Vincent Huard, Cheikh Ndiaye, M. Arabi, Narendra Parihar, X. Federspiel, Souhir Mhira, S. Mahapatra, Alain Bravaix:
Key parameters driving transistor degradation in advanced strained SiGe channels. IRPS 2018: 4-1
2015
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Nilesh Goel, P. Dubey, J. Kawa, S. Mahapatra:
Impact of time-zero and NBTI variability on sub-20nm FinFET based SRAM at low voltages. IRPS 2015: 5

2000 – 2009

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2007
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Sandip Debnath, S. Mahapatra, Ranjan Gangopadhyay:
Analysis of an optical packet switch with partially shared buffer and wavelength conversion. IET Commun. 1(4): 810-818 (2007)
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Muhammad Ashraful Alam, Haldun Kufluoglu, Dhanoop Varghese, S. Mahapatra:
A comprehensive model for PMOS NBTI degradation: Recent progress. Microelectron. Reliab. 47(6): 853-862 (2007)
2006
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T. S. Venkatesan, K. Deepika, S. Mahapatra:
The Jahn-Teller and pseudo-Jahn-Teller effects in the anion photoelectron spectroscopy of B3 cluster. J. Comput. Chem. 27(10): 1093-1100 (2006)
2005
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Muhammad Ashraful Alam, S. Mahapatra:
A comprehensive model of PMOS NBTI degradation. Microelectron. Reliab. 45(1): 71-81 (2005)
2003
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S. Mahapatra, S. Shukuri, Jeff Bude:
Substrate Bias Effect on Cycling Induced Performance Degradation of Flash EEPROMs. VLSI Design 2003: 223-226
2001
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Aatish Kumar, S. Mahapatra, R. Lal, V. Ramgopal Rao:
Multi-frequency transconductance technique for interface characterization of deep sub-micron SOI-MOSFETs. Microelectron. Reliab. 41(7): 1049-1051 (2001)
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G. Shrivastav, S. Mahapatra, V. Ramgopal Rao, J. Vasi, K. G. Anil, C. Fink, Walter Hansch, I. Eisele:
erformance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering. VLSI Design 2001: 475-478

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