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Azeez Bhavnagarwala
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2010 – 2019
- 2016
- [c7]Azeez Bhavnagarwala, Imran Iqbal, An Nguyen, David Ondricek, Vikas Chandra, Robert C. Aitken:
A 400mV active VMIN, 200mV retention VMIN, 2.8 GHz 64Kb SRAM with a 0.09 um2 6T bitcell in a 16nm FinFET CMOS process. VLSI Circuits 2016: 1-2 - 2014
- [c6]Yen-Tzu Lin, Brady Benware, Brian Stine, Azeez Bhavnagarwala:
Innovative practices session 2C: Advanced in yield learning. VTS 2014: 1 - 2010
- [c5]Azeez Bhavnagarwala, Shekhar Borkar, Takayasu Sakurai, Siva G. Narendra:
The semiconductor industry in 2025. ISSCC 2010: 534-535
2000 – 2009
- 2008
- [j5]Azeez J. Bhavnagarwala, Stephen Kosonocky, Carl Radens, Yuen H. Chan, Kevin Stawiasz, Uma Srinivasan, Steven P. Kowalczyk, Matthew M. Ziegler:
A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing. IEEE J. Solid State Circuits 43(4): 946-955 (2008) - 2003
- [j4]Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban:
Low-power circuits and technology for wireless digital systems. IBM J. Res. Dev. 47(2-3): 283-298 (2003) - 2002
- [j3]Rosana Rodríguez, James H. Stathis, Barry P. Linder, Steven P. Kowalczyk, Ching-Te Chuang, Rajiv V. Joshi, Gregory A. Northrop, Kerry Bernstein, Azeez J. Bhavnagarwala, Salvatore Lombardo
:
Analysis of the effect of the gate oxide breakdown on SRAM stability. Microelectron. Reliab. 42(9-11): 1445-1448 (2002) - 2001
- [j2]Azeez J. Bhavnagarwala, Xinghai Tang, James D. Meindl:
The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE J. Solid State Circuits 36(4): 658-665 (2001) - [c4]Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl:
Interconnect-centric Array Architectures for Minimum SRAM Access Time. ICCD 2001: 400-405 - 2000
- [j1]Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman
A minimum total power methodology for projecting limits on CMOS GSI. IEEE Trans. Very Large Scale Integr. Syst. 8(3): 235-251 (2000) - [c3]Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoor, James D. Meindl:
CMOS system-on-a-chip voltage scaling beyond 50nm. ACM Great Lakes Symposium on VLSI 2000: 7-12
1990 – 1999
- 1998
- [c2]Azeez J. Bhavnagarwala, Blanca Austin, James D. Meindl:
Minimum supply voltage for bulk Si CMOS GSI. ISLPED 1998: 100-102 - 1996
- [c1]Azeez J. Bhavnagarwala, Vivek De, Blanca Austin, James D. Meindl:
Circuit techniques for low-power CMOS GSI. ISLPED 1996: 193-196
Coauthor Index
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