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IEEE Micro, Volume 27, 2007
Volume 27, Number 1, January/February 2007
- David H. Albonesi:
Standing on Solid Ground. 5-6
- Shane Greenstein:
The High Cost of a Cheap Lesson. 7, 132-133
- Ronny Ronen, Antonio González
:
Guest Editors' Introduction: Micro's Top Picks from the Microarchitecture Conferences. 8-11 - Smruti R. Sarangi, Satish Narayanasamy
Patching Processor Design Errors with Programmable Hardware. 12-25 - Shan Lu
AVIO: Detecting Atomicity Violations via Access-Interleaving Invariants. 26-35 - George A. Reis, Jonathan Chang, David I. August:
Automatic Instruction-Level Software-Only Recovery. 36-47 - Min Xu, Rastislav Bodík, Mark D. Hill:
A Hardware Memory Race Recorder for Deterministic Replay. 48-55 - Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez
On-Chip Optical Technology in Future Bus-Based Multicore Designs. 56-66 - Austen McDonald, Brian D. Carlstrom, JaeWoong Chung, Chi Cao Minh, Hassan Chafi, Christos Kozyrakis, Kunle Olukotun:
Transactional Memory: The Hardware-Software Interface. 67-76 - Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
3D Integration for Introspection. 77-83 - Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith:
A Top-Down Approach to Architecting CPI Component Performance Counters. 84-93 - Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt:
Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication. 94-104 - Tingting Sha, Milo M. K. Martin, Amir Roth:
NoSQ: Store-Load Communication without a Store Queue. 106-113 - Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner:
SODA: A High-Performance DSP Architecture for Software-Defined Radio. 114-123
- Richard H. Stern:
West Coast Federal Appeals Court Upholds Chip Protection Act Violation Finding. 124-126
- Richard Mateosian:
Economics. 128-130
- Philip G. Emma:
Reinventing Entrepreneurial Inventing for the 21st Century. 134-136
Volume 27, Number 2, March/April 2007
- David H. Albonesi:
Editor in Chief's Message: Truly "hot" chips - Do we still care? 4-5
- Shane Greenstein:
Wagging Wikipedia's long tail. 6, 79
- John Kubiatowicz, Howard Sachs:
Guest Editors' Introduction: Hot Chips 18. 7-9 - Pat Conway, Bill Hughes:
The AMD Opteron Northbridge Architecture. 10-21 - Sivakumar Radhakrishnan, Sundaram Chinthamani, Kai Cheng:
The Blackford Northbridge Chipset for the Intel 5000. 22-33 - Bevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric W. Work, Jeremy W. Webb, Michael A. Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung:
AsAP: A Fine-Grained Many-Core Platform for DSP Applications. 34-45 - John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic:
RAMP: Research Accelerator for Multiple Processors. 46-57 - Arjan Bink, Richard York:
ARM996HS: The First Licensable, Clockless 32-Bit Processor Core. 58-68 - Tse-Yu Yeh:
Low-Power, High-Performance Architecture of the PWRficient Processor Family. 69-78
- Richard H. Stern:
Coming down the home stretch in the Rambus standardization skullduggery saga: To levy or not to levy royalties. 80-82
- Richard Mateosian:
Looking Back. 83-85
- Philip G. Emma:
Supercharging Your Creative Skills. 86-88
Volume 27, Number 3, May/June 2007
- David H. Albonesi:
More Hot Stuff. 4-5
- Shane Greenstein:
Did the Price of the Internet Drop? 6-7
- Tim Harris, Adrián Cristal
Transactional Memory: An Overview. 8-29 - Gabriel H. Loh, Yuan Xie, Bryan Black:
Processor Design in 3D Die-Stacking Technologies. 31-48 - David M. Brooks, Robert P. Dick, Russ Joseph, Li Shang:
Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors. 49-62 - Kenneth Hoste, Lieven Eeckhout:
Microarchitecture-Independent Workload Characterization. 63-72 - Benjamin C. Lee, David M. Brooks:
Spatial Sampling and Regression Strategies. 74-93 - Serag GadelRab:
10-Gigabit Ethernet Connectivity for Computer Servers. 94-105
- Richard H. Stern:
Antitrust Division Gives IEEE Standard Setters the Okay to Ask Patentees How RAND They Are. 106-109
- Philip G. Emma:
Arcane Facts and New Words: Expanding Your Creative Talent. 110-112
Volume 27, Number 4, July/August 2007
- David H. Albonesi:
Mixing It Up. 3-4
- Shane Greenstein:
The 15-Billion-Dollar Broadband Bonus. 5, 58
- Assaf Shacham
Building Ultralow-Latency Interconnection Networks Using Photonic Integration. 6-20 - Li Zhao, Ravi R. Iyer, Jaideep Moses, Ramesh Illikkal, Srihari Makineni, Donald Newell:
Exploring Large-Scale CMP Architectures Using ManySim. 21-33 - Jianwei Chen, Michel Dubois, Per Stenström:
SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators. 34-48 - Iván González
Self-Reconfigurable Embedded Systems on Low-Cost FPGAs. 49-57
- Richard Mateosian:
Thinking about Technology. 59-61
- Philip G. Emma:
Innovation or Notoriety? 62-64
Volume 27, Number 5, September/October 2007
- Partha Kundu, Li-Shiuan Peh:
Guest Editors' Introduction: On-Chip Interconnects for Multicores. 3-5 - Thomas William Ainsworth, Timothy Mark Pinkston:
Characterizing the Cell EIB On-Chip Network. 6-14 - David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, Bruce Edwards, Carl Ramey, Matthew Mattina, Chyi-Chang Miao, John F. Brown III, Anant Agarwal:
On-Chip Interconnection Architecture of the Tile Processor. 15-31 - Mike Butts:
Synchronization through Communication in a Massively Parallel Processor Array. 32-40 - Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger:
On-Chip Interconnection Networks of the TRIPS Chip. 41-50 - Yatin Hoskote, Sriram R. Vangal, Arvind P. Singh, Nitin Borkar, Shekhar Borkar:
A 5-GHz Mesh Interconnect for a Teraflops Processor. 51-61 - David Arditti Ilitzky, Jeffrey D. Hoffman, Anthony Chun, Brando Perez Esparza:
Architecture of the Scalable Communications Core's Network on Chip. 62-74 - Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini:
Bringing NoCs to 65 nm. 75-85 - Ümit Y. Ogras, Radu Marculescu, Hyung Gyu Lee, Puru Choudhary, Diana Marculescu, Michael Kaufman, Peter Nelson:
Challenges and Promising Results in NoC Prototyping Using FPGAs. 86-95 - John D. Owens, William J. Dally, Ron Ho, Doddaballapur Narasimha-Murthy Jayasimha, Stephen W. Keckler, Li-Shiuan Peh:
Research Challenges for On-Chip Interconnection Networks. 96-108
- Richard H. Stern:
Federal Appeals Court Sees Potential Antitrust Violation in Standardization Skullduggery. 109-110
- Shane Greenstein:
Dog Days for Broadband. 111-112
Volume 27, Number 6, November/December 2007
- David H. Albonesi:
Productive and Healthy Debate. 6 - Shane Greenstein:
Innovation at the Edges. 8-10 - Richard H. Stern:
Supreme Court to Hear Semiconductor Chip Patent "Exhaustion" Case. 11-13 - Joel S. Emer, Mark D. Hill, Yale N. Patt, Joshua J. Yi, Derek Chiou, Resit Sendag:
Single-Threaded vs. Multithreaded: Where Should We Focus? 14-24 - Shay Gueron
Where Does Security Stand? New Vulnerabilities vs. Trusted Computing. 25-35 - Antonio González
Reliability: Fallacy or Reality? 36-45 - Kevin Skadron
Low-Power Design and Temperature Management. 46-57 - Richard Mateosian:
Advice for Investigators. 60-61 - Philip G. Emma:
You're Invited to a Party! (How To Hold a Collaborative IP-Development Session). 62-64
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