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Microprocessors and Microsystems, Volume 42
Volume 42, May 2016
- Sharareh Zamanzadeh, Ali Jahanian
:
Higher security of ASIC fabrication process against reverse engineering attack using automatic netlist encryption methodology. 1-9 - Jadav Chandra Das, Debashis De
Novel low power reversible binary incrementer design using quantum-dot cellular automata. 10-23 - Marta Ortín-Obón
Analysis of network-on-chip topologies for cost-efficient chip multiprocessors. 24-36 - Sreram Balasubramaniyan, Seshadhri Srinivasan
Design and verification of Cyber-Physical Systems using TrueTime, evolutionary optimization and UPPAAL. 37-48 - Prabhakar Mishra, Harshavardhan Vajjramatti, Abijeeth Rai, Kirankumar Mangond, Nidhi Anantharajaiah, J. K. Kishore:
Computational architectures for sonar array processing in autonomous rovers. 49-69 - Alejandro Masrur, Michal Kit, Vladimír Matena
Component-based design of cyber-physical applications with safety-critical requirements. 70-86 - Madaín Pérez Patricio
An FPGA stereo matching unit based on fuzzy logic. 87-99 - Young-Ho Gong, Jae Min Kim, Sung Kyu Lim
Exploration of temperature-aware refresh schemes for 3D stacked eDRAM caches. 100-112 - Ali Azarpeyvand
Fast and accurate architectural vulnerability analysis for embedded processors using Instruction Vulnerability Factor. 113-126 - Pascal Cotret
Protection of heterogeneous architectures on FPGAs: An approach based on hardware firewalls. 127-141 - Erik Hertz, Bertil Svensson
Combining the parabolic synthesis methodology with second-degree interpolation. 142-155 - Sergio Johann Filho, Matheus T. Moreira, Leandro S. Heck, Ney Laert Vilar Calazans
A processor for IoT applications: An assessment of design space and trade-offs. 156-164 - Ali Azarian
Pipelining data-dependent tasks in FPGA-based multicore architectures. 165-179 - Fatemeh Nasiri
Reconfigurable multicast routing for Networks on Chip. 180-189
- Pao-Ann Hsiung, Yuan-Hao Chang, Chun-Hsian Huang, Tei-Wei Kuo
Introduction to the special issue on smart reconfigurable system modeling, design, and implementation. 190 - Wei-Kai Cheng, Yen-Heng Ciou, Po-Yuan Shen:
Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration. 191-199 - Gang Chen, Biao Hu, Kai Huang, Alois C. Knoll
Reconfigurable cache for real-time MPSoCs: Scheduling and implementation. 200-214 - Wen-Chung Tsai, Wei-De Chen, Ying-Cherng Lan, Yu Hen Hu, Sao-Jie Chen
A BiNoC architecture - aware task allocation and communication scheduling scheme. 215-226 - Trong-Yen Lee, Chi-Han Huang, Wei-Cheng Chen, Min-Jea Liu:
A low-area dynamic reconfigurable MDC FFT processor design. 227-234 - Hung-Lin Chao
A fair energy resource allocation strategy for micro grid. 235-244
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