default search action
International Journal of Reconfigurable Computing, Volume 2012
Volume 2012, 2012
- Ilia A. Lebedev
, Christopher W. Fletcher, Shaoyi Cheng, James C. Martin, Austin Doupnik, Daniel Burke, Mingjie Lin, John Wawrzynek:
Exploring Many-Core Design Templates for FPGAs and ASICs. 439141:1-439141:15 - Manuel Saldaña, Arun Patel, Hao Jun Liu, Paul Chow:
Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms. 127302:1-127302:10 - Sascha Mühlbach, Andreas Koch:
A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection. 342625:1-342625:14 - Tom Davidson
Dynamic Circuit Specialisation for Key-Based Encryption Algorithms and DNA Alignment. 716984:1-716984:13 - Kaveh Aasaraai, Andreas Moshovos:
NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution. 915178:1-915178:12 - Joshua S. Monson, Michael J. Wirthlin, Brad L. Hutchings:
A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform. 850487:1-850487:11 - Angelo Kuti Lusala
Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks. 474765:1-474765:16 - Mariusz Grad, Christian Plessl
On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors. 418315:1-418315:21 - William V. Kritikos, Andrew G. Schmidt, Ron Sass, Erik K. Anderson, Matthew French:
Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip. 872610:1-872610:11 - Stefan Wildermann, Josef Angermeier, Eugen Sibirko, Jürgen Teich:
Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures. 608312:1-608312:12 - Zain-ul-Abdin
Occam-pi for Programming of Massively Parallel Reconfigurable Architectures. 504815:1-504815:17 - Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker
Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices. 219717:1-219717:10 - Ali Akbar Zarezadeh, Christophe Bobda:
Hardware Middleware for Person Tracking on Embedded Distributed Smart Cameras. 615824:1-615824:10 - Christian de Schryver
A Hardware Efficient Random Number Generator for Nonuniform Distributions with Arbitrary Precision. 675130:1-675130:11 - Wim Vanderbauwhede
Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application. 507173:1-507173:16 - Ra Inta
The "Chimera": An Off-The-Shelf CPU/GPGPU/FPGA Hybrid Computing Platform. 241439:1-241439:10 - Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu:
Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography. 360242:1-360242:9 - Christoph Starke, Vasco Grossmann, Lars Wienbrandt
Optimizing Investment Strategies with the Reconfigurable Hardware Platform RIVYERA. 646984:1-646984:10 - Florent Bernard, Viktor Fischer, Crina Costea, Robert Fouquet:
Implementation of Ring-Oscillators-Based Physical Unclonable Functions with Independent Bits in the Response. 168961:1-168961:13 - Juan Fernando Eusse Giraldo, Nahri Moreano
A Protein Sequence Analysis Hardware Accelerator Based on Divergences. 201378:1-201378:19 - Lu Wan, Chen Dong, Deming Chen
A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance. 163542:1-163542:17 - Andrew G. Schmidt, William V. Kritikos, Shanyuan Gao
An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing. 564704:1-564704:15 - Khaled Benkrid, Ali Akoglu
High Performance Biological Pairwise Sequence Alignment: FPGA versus GPU versus Cell BE versus GPP. 752910:1-752910:15 - Esam El-Araby
A Convolve-And-MErge Approach for Exact Computations on High-Performance Reconfigurable Computers. 925864:1-925864:14 - Kamana Sigdel, Carlo Galuzzi, Koen Bertels, Mark Thompson, Andy D. Pimentel
Evaluation of Runtime Task Mapping Using the rSesame Framework. 234230:1-234230:17 - Khaled Benkrid, Esam El-Araby
High-Performance Reconfigurable Computing. 104963:1-104963:2 - Jones Yudi Mori
An FPGA-Based Omnidirectional Vision Sensor for Motion Detection on Mobile Robots. 148190:1-148190:16 - Alba Sandyra Bezerra Lopes
A Memory Hierarchy Model Based on Data Reuse for Full-Search Motion Estimation on High-Definition Digital Videos. 473725:1-473725:10 - Johanna Sepúlveda, Ricardo Pires
QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection. 578363:1-578363:10 - Alexander Thomas, Michael Rückauer, Jürgen Becker
HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture. 832531:1-832531:17 - David Castells-Rufas
Performance Analysis Techniques for Multi-Soft-Core and Many-Soft-Core Systems. 736347:1-736347:14 - Supriya Aggarwal
Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency. 185784:1-185784:8 - David H. K. Hoe
Cellular Automata-Based Parallel Random Number Generators Using FPGAs. 219028:1-219028:13 - Wilmar Carvajal Ossa, Wilhelmus A. M. Van Noije:
An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H. 786205:1-786205:17 - Matthias Kühnle, André Wagner, Alisson Vasconcelos de Brito
Modeling and Implementation of a Power Estimation Methodology for SystemC. 439727:1-439727:12 - Daniel Palomino
Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders. 813023:1-813023:10 - Christoph Roth, Joachim Meyer, Michael Rückauer, Oliver Sander, Jürgen Becker
Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels. 729786:1-729786:13 - Claudia Feregrino, Miguel Arias, Kris Gaj, Viktor K. Prasanna, Marco D. Santambrogio
Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10). 319827:1-319827:2 - Gustavo Sanchez
DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation. 186057:1-186057:12 - Hanaa M. Hussain, Khaled Benkrid, Ali Ebrahim
Novel Dynamic Partial Reconfiguration Implementation of K-Means Clustering on FPGAs: Comparative Results with GPPs and GPUs. 135926:1-135926:15 - Diana Göhringer, Lukas Meder
Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration. 298561:1-298561:14 - Rafael A. Arce-Nazario
Multidimensional Costas Arrays and Their Enumeration Using GPUs and FPGAs. 196761:1-196761:9 - Lyndon Judge
A Hardware-Accelerated ECDLP with High-Performance Modular Multiplication. 439021:1-439021:14 - Andrew G. Schmidt, Neil Steiner, Matthew French, Ron Sass:
HwPMI: An Extensible Performance Monitoring Infrastructure for Improving Hardware Design and Productivity on FPGAs. 162404:1-162404:12 - Élvio Carlos Dutra e Silva Júnior, Leandro Soares Indrusiak
A Programmable Look-Up Table-Based Interpolator with Nonuniform Sampling Scheme. 647805:1-647805:14 - Michael Schaeferling, Ulrich Hornung, Gundolf Kiefer:
Object Recognition and Pose Estimation on Embedded Hardware: SURF-Based System Designs Accelerated by FPGA Logic. 368351:1-368351:16 - Zoltán Endre Rákossy
High-Level Design Space and Flexibility Exploration for Adaptive, Energy-Efficient WCDMA Channel Estimation Architectures. 961950:1-961950:20 - Eduardo Romero-Aguirre, Ramón Parra-Michel, Roberto Carrasco-Alvarez, Aldo G. Orozco-Lugo:
Configurable Transmitter and Systolic Channel Estimator Architectures for Data-Dependent Superimposed Training Communications Systems. 236372:1-236372:13 - George Sobral Silveira, Alisson Vasconcelos de Brito
Open SystemC Simulator with Support for Power Gating Design. 793190:1-793190:8
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-16 22:27 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: