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ACM Transactions on Reconfigurable Technology and Systems, Volume 10
Volume 10, Number 1, December 2016
- Nicholas Wulf, Alan D. George
, Ann Gordon-Ross:
A Framework for Evaluating and Optimizing FPGA-Based SoCs for Aerospace Computing. 1:1-1:29 - Justin Richardson, Alan D. George
Analysis of Fixed, Reconfigurable, and Hybrid Devices with Computational, Memory, I/O, & Realizable-Utilization Metrics. 2:1-2:21 - Hung-Lin Chao
Dynamic Task Mapping with Congestion Speculation for Reconfigurable Network-on-Chip. 3:1-3:25 - Bertrand Le Gal, Yérom-David Bromberg, Laurent Réveillère, Jigar Solanki:
A Flexible SoC and Its Methodology for Parser-Based Applications. 4:1-4:23 - Yeyong Pang
A Microcoded Kernel Recursive Least Squares Processor Using FPGA Technology. 5:1-5:22 - Qing Y. Tang, Mohammed A. S. Khalid:
Acceleration of k-Means Algorithm Using Altera SDK for OpenCL. 6:1-6:19 - Henry Wong, Vaughn Betz, Jonathan Rose:
Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System. 7:1-7:22 - Bita Darvish Rouhani, Azalia Mirhoseini, Ebrahim M. Songhori, Farinaz Koushanfar
Automated Real-Time Analysis of Streaming Big and Dense Data on Reconfigurable Platforms. 8:1-8:22 - Alban Bourge, Olivier Muller, Frédéric Rousseau:
Generating Efficient Context-Switch Capable Circuits through Autonomous Design Flow. 9:1-9:23
Volume 10, Number 2, April 2017
- João M. P. Cardoso
Introduction to the Special Section on FPL 2015. 10:1-10:2 - Jin Hee Kim, Jason Helge Anderson:
Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow. 11:1-11:23 - Pavel Burovskiy
Efficient Assembly for High-Order Unstructured FEM Meshes (FPL 2015). 12:1-12:22 - Hsin-Jung Yang
(FPL 2015) Scavenger: Automating the Construction of Application-Optimized Memory Hierarchies. 13:1-13:23 - Nachiket Kapre, Jan Gray:
Hoplite: A Deflection-Routed Directional Torus NoC for FPGAs. 14:1-14:24
- Philip Heng Wai Leong
The First 25 Years of the FPL Conference: Significant Papers. 15:1-15:17 - Shigeyuki Takano:
Performance Scalability of Adaptive Processor Architecture. 16:1-16:22
Volume 10, Number 3, July 2017
- Zhiqiang Liu, Yong Dou, Jingfei Jiang, Jinwei Xu, Shijie Li, Yongmei Zhou, Yingnan Xu:
Throughput-Optimized FPGA Accelerator for Deep Convolutional Neural Networks. 17:1-17:23 - Tomohiro Ueno
Bandwidth Compression of Floating-Point Numerical Data Streams for FPGA-Based High-Performance Computing. 18:1-18:22 - Charles Eric LaForest, Jason Helge Anderson:
Microarchitectural Comparison of the MXP and Octavo Soft-Processor FPGA Overlays. 19:1-19:25 - Chongyan Gu
Improved Reliability of FPGA-Based PUF Identification Generator Design. 20:1-20:23 - Adrien Prost-Boucle
Efficient and Versatile FPGA Acceleration of Support Counting for Stream Mining of Sequences and Frequent Itemsets. 21:1-21:25 - Ilian Tili, Kalin Ovtcharov, J. Gregory Steffan:
Reducing the Performance Gap between Soft Scalar CPUs and Custom Hardware with TILT. 22:1-22:23 - Nicholas Wulf, Alan D. George
Optimizing FPGA Performance, Power, and Dependability with Linear Programming. 23:1-23:23 - Heinrich Riebler
Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. 24:1-24:23
Volume 10, Number 4, December 2017
- Eduardo A. Gerlein
Network on Chip Architecture for Multi-Agent Systems in FPGA. 25:1-25:22 - Nicholas J. Fraser, JunKyu Lee
FPGA Implementations of Kernel Normalised Least Mean Squares Processors. 26:1-26:20 - Thiem Van Chu, Shimpei Sato, Kenji Kise:
Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA. 27:1-27:27 - Masato Yoshimi
Pipelined Parallel Join and Its FPGA-Based Acceleration. 28:1-28:28 - Pieter Fabry, David Thomas:
Efficient Reconfigurable Architecture for Pricing Exotic Options. 29:1-29:22
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