default search action
24th RSP 2013: Montreal, QC, Canada
- Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, RSP 2013, Montreal, QC, Canada, October 3-4, 2013. IEEE 2013
Technical Session 1: FPGA Technologies
- Qingshan Tang, Matthieu Tuna, Habib Mehrez:
Routing algorithm for multi-FPGA based systems using multi-point physical tracks. 2-8 - David Uliana, Krzysztof Kepa
, Peter Athanas:
FPGA-based HPC application design for non-experts. 9-15 - Konstantin Nasartschuk, Rainer Herpers
Visual exploration of changing FPGA architectures in the VTR project. 16-22
Session 2: Network-on-Chip
- César A. M. Marcon
An implementation of a distributed fault-tolerant mechanism for 2D mesh NoCs. 24-29 - Takashi Nakada, Shinobu Miwa, Keisuke Y. Yano, Hiroshi Nakamura
Performance modeling for designing NoC-based multiprocessors. 30-36 - Matheus T. Moreira, Felipe G. Magalhaes, Matheus Gibiluka, Fabiano Hessel
BaBaNoC: An asynchronous network-on-chip described in Balsa. 37-43 - Kazem Cheshmi, Mohammadreza Soltaniyeh, Siamak Mohammadi
Quota setting router architecture for quality of service in GALS NoC. 44-50 - Otávio Alcântara de Lima Júnior, Virginie Fresse, Frédéric Rousseau:
FlexOE: A congestion-aware routing algorithm for NoCs. 51-57
Session 3: Model-Based, Verifications and Applications
- Vincent Gaudel, Frank Singhoff, Alain Plantec, Jérôme Hugues, Pierre Dissaux, Jérôme Legrand:
Enforcing software engineering tools interoperability: An example with AADL subsets. 59-65 - Nico Adler, Stefan Otten, Markus Mohrhard, Klaus D. Müller-Glaser:
Rapid safety evaluation of hardware architectural designs compliant with ISO 26262. 66-72 - Olfat El-Mahi, Gilles Pesant, Gabriela Nicolescu, Giovanni Beltrame:
Embedded system verification through constraint-based scheduling. 73-79 - Norbert Druml, Manuel Menghin, Daniel Kroisleitner, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid:
Emulation-based design evaluation of reader/smart card systems. 80-86 - Purushotham Murugappa, Vianney Lapotre, Amer Baghdadi
Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes. 87-93 - Vinicius Bohrer, Ramon Fernandes, César A. M. Marcon
A flexible framework for modeling and simulation of multipurpose wireless networks. 94-100
Session 4: Multi-Processor Systems-on-Chip
- Riccardo Cattaneo
SMASH: A heuristic methodology for designing partially reconfigurable MPSoCs. 102-108 - Tiago Rogério Mück, Antônio Augusto Fröhlich
Seamless integration of HW/SW components in a HLS-based SoC design environment. 109-115 - Ricardo Santos, Renan A. Marks
A framework for instruction encoding designs on embedded processors. 116-122 - Silvia Lovergine, Antonino Tumeo
YAPPA: A compiler-based parallelization framework for irregular applications on MPSoCs. 123-129 - Alexandra Aguiar, Sergio Johann Filho, Felipe Gohring de Magalhaes, Fabiano Hessel
Customizable RTOS to support communication infrastructures and to improve design space exploration in MPSoCs. 130-135 - Shakith Fernando, Firew Siyoum, Yifan He, Akash Kumar
MAMPSx: A design framework for rapid synthesis of predictable heterogeneous MPSoCs. 136-142
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-18 18:34 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: